PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 11:34:49 1998 par -w -ol 1 -i 4 -t 1 -n 5 -s 5 map.ncd ../p3.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 5 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 790036 Placer score = 504823 Placer score = 455629 Placer score = 391893 Placer score = 352523 Placer score = 344856 Placer score = 313529 Placer score = 297418 Placer score = 283129 Placer score = 271210 Placer score = 265519 Placer score = 261311 Placer score = 261120 Placer score = 259151 Placer score = 255981 Placer score = 252864 Placer score = 251473 Placer score = 250229 Finished Constructive Placer. REAL time: 2 mins 9 secs Writing design to file "../p3.dir/1_1_5.ncd". Total REAL time to Placer completion: 2 mins 10 secs Total CPU time to Placer completion: 2 mins 9 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 25 secs Starting iterative routing. Routing active signals. End of iteration 1 3350 successful; 52 unrouted; (5383114) REAL time: 5 mins 30 secs End of iteration 2 3402 successful; 0 unrouted; (2097150) REAL time: 7 mins 51 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 7 timing errors. Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (735008) REAL time: 10 mins 16 secs End of iteration 4 3402 successful; 0 unrouted; (576483) REAL time: 12 mins 23 secs Writing design to file "../p3.dir/1_1_5.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 7 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (523454) REAL time: 13 mins 36 secs Writing design to file "../p3.dir/1_1_5.ncd". Total REAL time: 13 mins 36 secs Total CPU time: 13 mins 35 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 13 mins 40 secs Total CPU time to Router completion: 13 mins 38 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 162424 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.930 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.172 ns The Maximum Pin Delay is: 26.560 ns The Average Connection Delay on the 10 Worst Nets is: 23.107 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3094 285 23 0 0 0 Timing Score: 523454 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 35.969ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_5.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins 47 secs Total CPU time to PAR completion: 13 mins 45 secs PAR done.