PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 14:08:15 1998 par -w -ol 4 -i 4 -t 1 -n 5 -s 5 map.ncd ../p4.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 2 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 13 secs Finished initial Placement phase. REAL time: 14 secs Starting Constructive Placer. REAL time: 15 secs Placer score = 799264 Placer score = 551354 Placer score = 501945 Placer score = 477070 Placer score = 447908 Placer score = 423692 Placer score = 406403 Placer score = 387652 Placer score = 378227 Placer score = 339933 Placer score = 337815 Placer score = 319122 Placer score = 301077 Placer score = 292643 Placer score = 277346 Placer score = 274217 Placer score = 267683 Placer score = 251952 Placer score = 243440 Placer score = 237113 Placer score = 222175 Placer score = 220047 Placer score = 216361 Placer score = 210983 Placer score = 203610 Placer score = 199697 Placer score = 198430 Placer score = 195142 Placer score = 194079 Placer score = 193158 Placer score = 191773 Placer score = 190290 Placer score = 188908 Placer score = 187329 Placer score = 187113 Placer score = 186664 Placer score = 185405 Placer score = 184825 Placer score = 184445 Placer score = 184265 Placer score = 184145 Finished Constructive Placer. REAL time: 11 mins 4 secs Writing design to file "../p4.dir/4_4_2.ncd". Starting Optimizing Placer. REAL time: 11 mins 4 secs Optimizing .. Swapped 10 comps. Xilinx Placer [3] 184015 REAL time: 11 mins 36 secs Finished Optimizing Placer. REAL time: 11 mins 36 secs Writing design to file "../p4.dir/4_4_2.ncd". Total REAL time to Placer completion: 11 mins 37 secs Total CPU time to Placer completion: 11 mins 19 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 11 mins 54 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2352161) REAL time: 12 mins 27 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (31996) REAL time: 13 mins 52 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (19871) REAL time: 16 mins 26 secs End of iteration 4 3402 successful; 0 unrouted; (17961) REAL time: 18 mins 33 secs Writing design to file "../p4.dir/4_4_2.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (17961) REAL time: 20 mins 27 secs Writing design to file "../p4.dir/4_4_2.ncd". Total REAL time: 20 mins 27 secs Total CPU time: 20 mins 1 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 20 mins 30 secs Total CPU time to Router completion: 20 mins 4 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 9111 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.113 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.147 ns The Maximum Pin Delay is: 21.240 ns The Average Connection Delay on the 10 Worst Nets is: 17.036 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3221 177 4 0 0 0 Timing Score: 17961 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 24.087ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p4.dir/4_4_2.ncd". All signals are completely routed. Total REAL time to PAR completion: 20 mins 40 secs Total CPU time to PAR completion: 20 mins 12 secs PAR done.