PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 14:28:55 1998 par -w -ol 4 -i 4 -t 1 -n 5 -s 5 map.ncd ../p4.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 3 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 10 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 11 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 723904 Placer score = 555097 Placer score = 523185 Placer score = 465056 Placer score = 427497 Placer score = 419905 Placer score = 386022 Placer score = 380636 Placer score = 353781 Placer score = 336468 Placer score = 323988 Placer score = 320548 Placer score = 290101 Placer score = 277004 Placer score = 270617 Placer score = 257415 Placer score = 242744 Placer score = 238265 Placer score = 228186 Placer score = 218591 Placer score = 211730 Placer score = 203765 Placer score = 200325 Placer score = 195491 Placer score = 192056 Placer score = 190946 Placer score = 190863 Placer score = 186355 Placer score = 185172 Placer score = 184627 Placer score = 184322 Placer score = 183566 Placer score = 183056 Placer score = 180347 Placer score = 179193 Placer score = 178123 Placer score = 177107 Placer score = 176595 Placer score = 176447 Placer score = 176146 Placer score = 176096 Placer score = 176057 Placer score = 175816 Placer score = 175606 Placer score = 174958 Placer score = 174617 Placer score = 174446 Placer score = 174386 Finished Constructive Placer. REAL time: 9 mins 9 secs Writing design to file "../p4.dir/4_4_3.ncd". Starting Optimizing Placer. REAL time: 9 mins 9 secs Optimizing .. Swapped 16 comps. Xilinx Placer [4] 174127 REAL time: 9 mins 40 secs Finished Optimizing Placer. REAL time: 9 mins 40 secs Writing design to file "../p4.dir/4_4_3.ncd". Total REAL time to Placer completion: 9 mins 41 secs Total CPU time to Placer completion: 9 mins 34 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 10 mins 2 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2167322) REAL time: 10 mins 41 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (30629) REAL time: 12 mins 32 secs Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (13642) REAL time: 15 mins 37 secs End of iteration 4 3402 successful; 0 unrouted; (9196) REAL time: 18 mins 10 secs Writing design to file "../p4.dir/4_4_3.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (9196) REAL time: 20 mins Writing design to file "../p4.dir/4_4_3.ncd". Total REAL time: 20 mins 1 secs Total CPU time: 19 mins 27 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 20 mins 5 secs Total CPU time to Router completion: 19 mins 30 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 5890 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.955 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.180 ns The Maximum Pin Delay is: 17.183 ns The Average Connection Delay on the 10 Worst Nets is: 15.551 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3263 139 0 0 0 0 Timing Score: 9196 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.474ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p4.dir/4_4_3.ncd". All signals are completely routed. Total REAL time to PAR completion: 20 mins 16 secs Total CPU time to PAR completion: 19 mins 39 secs PAR done.