PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 14:49:12 1998 par -w -ol 4 -i 4 -t 1 -n 5 -s 5 map.ncd ../p4.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 4 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 10 secs Finished initial Timing Analysis. REAL time: 14 secs Starting initial Placement phase. REAL time: 15 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 16 secs Placer score = 795088 Placer score = 535835 Placer score = 492670 Placer score = 445449 Placer score = 423620 Placer score = 391839 Placer score = 377774 Placer score = 357894 Placer score = 340879 Placer score = 335132 Placer score = 312988 Placer score = 288955 Placer score = 272358 Placer score = 264484 Placer score = 257333 Placer score = 244572 Placer score = 231133 Placer score = 218635 Placer score = 210559 Placer score = 209152 Placer score = 200582 Placer score = 198907 Placer score = 198685 Placer score = 193523 Placer score = 192279 Placer score = 189391 Placer score = 189100 Placer score = 186996 Placer score = 186489 Placer score = 185047 Placer score = 182715 Placer score = 181109 Placer score = 180703 Placer score = 180223 Placer score = 179962 Placer score = 179722 Placer score = 179586 Placer score = 179288 Placer score = 178850 Placer score = 178340 Placer score = 178100 Placer score = 178054 Finished Constructive Placer. REAL time: 11 mins 44 secs Writing design to file "../p4.dir/4_4_4.ncd". Starting Optimizing Placer. REAL time: 11 mins 44 secs Optimizing .. Swapped 13 comps. Xilinx Placer [5] 177874 REAL time: 12 mins 16 secs Finished Optimizing Placer. REAL time: 12 mins 16 secs Writing design to file "../p4.dir/4_4_4.ncd". Total REAL time to Placer completion: 12 mins 17 secs Total CPU time to Placer completion: 11 mins 57 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 12 mins 34 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1846206) REAL time: 13 mins 5 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (35680) REAL time: 14 mins 8 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (15853) REAL time: 15 mins 59 secs End of iteration 4 3402 successful; 0 unrouted; (12894) REAL time: 17 mins 29 secs Writing design to file "../p4.dir/4_4_4.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (10164) REAL time: 18 mins 50 secs Writing design to file "../p4.dir/4_4_4.ncd". Total REAL time: 18 mins 50 secs Total CPU time: 18 mins 29 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 18 mins 53 secs Total CPU time to Router completion: 18 mins 32 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 10907 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.029 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.186 ns The Maximum Pin Delay is: 17.613 ns The Average Connection Delay on the 10 Worst Nets is: 15.090 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3263 139 0 0 0 0 Timing Score: 10164 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 21.799ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p4.dir/4_4_4.ncd". All signals are completely routed. Total REAL time to PAR completion: 19 mins 2 secs Total CPU time to PAR completion: 18 mins 41 secs PAR done.