PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Wed Oct 07 16:13:53 1998 par -w -ol 2 -i 2 -d 0 map.ncd bdes.ncd bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 15 secs Finished initial Placement phase. REAL time: 15 secs Starting Constructive Placer. REAL time: 16 secs Placer score = 650717 Placer score = 540365 Placer score = 525783 Placer score = 477412 Placer score = 445208 Placer score = 437080 Placer score = 399221 Placer score = 390204 Placer score = 367060 Placer score = 349572 Placer score = 341857 Placer score = 328474 Placer score = 296327 Placer score = 286231 Placer score = 283095 Placer score = 267469 Placer score = 253539 Placer score = 246123 Placer score = 233354 Placer score = 228723 Placer score = 222112 Placer score = 219504 Placer score = 212084 Placer score = 206372 Placer score = 201960 Placer score = 198339 Placer score = 196680 Placer score = 196575 Placer score = 194986 Placer score = 193978 Placer score = 193760 Placer score = 191793 Placer score = 191226 Placer score = 190103 Placer score = 189460 Placer score = 189190 Placer score = 188800 Finished Constructive Placer. REAL time: 6 mins 31 secs Writing design to file "bdes.ncd". Starting Optimizing Placer. REAL time: 6 mins 32 secs Optimizing .. Swapped 30 comps. Xilinx Placer [1] 188174 REAL time: 7 mins 3 secs Finished Optimizing Placer. REAL time: 7 mins 3 secs Writing design to file "bdes.ncd". Total REAL time to Placer completion: 7 mins 4 secs Total CPU time to Placer completion: 7 mins 3 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 7 mins 21 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1458062) REAL time: 7 mins 53 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (52986) REAL time: 9 mins 7 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "bdes.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (52686) REAL time: 10 mins 34 secs Writing design to file "bdes.ncd". Total REAL time: 10 mins 35 secs Total CPU time: 10 mins 33 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 10 mins 38 secs Total CPU time to Router completion: 10 mins 36 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 28752 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.892 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.186 ns The Maximum Pin Delay is: 19.025 ns The Average Connection Delay on the 10 Worst Nets is: 15.460 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3296 106 0 0 0 0 Timing Score: 52686 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 28.415ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "bdes.ncd". All signals are completely routed. Total REAL time to PAR completion: 10 mins 46 secs Total CPU time to PAR completion: 10 mins 44 secs PAR done.