SCHEMATIC START ;
TIMEGRP "clk" = BEL "bootstrap/dma_cnt/iq_reg<19>" BEL 
"interrupt_source/q_reg<2>" BEL "interrupt_source/divide_reg<1>" BEL 
"bootstrap/wr_source/r10/q_reg<2>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<11>" BEL 
"memory_interface/rcp_1553_cs_n_reg" BEL 
"synthesizer_interface/synth/shift_reg_reg<20>" BEL 
"antenna_interface/ant/shift_reg_reg<0>" BEL "audio_interface/aud/cycle_reg<2>" 
BEL "tod_receiver/tod_receiver/manchester_decoder/timeout_reg<4>" BEL 
"fan_interface/pwm/shift_reg_reg<9>" BEL "bootstrap/rx/sreg_reg<6>" BEL 
"rtc_divide/clock_reg<5>" BEL "external_port/rcp_reg1_reg<FM_HI_BAND>" BEL 
"audio_interface/aud/comm_sreg_reg<5>" BEL 
"synthesizer_interface/synth/ser_clk_reg" BEL 
"synthesizer_interface/sync_high/wren_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<8>" BEL 
"iic_bus_interface/iic/clock_reg<5>" BEL "bootstrap/incr_addr_reg" BEL 
"bootstrap/tx/baud_reg<7>" BEL "audio_interface/aud/clock_reg<1>" BEL 
"synthesizer_interface/synth/shift_reg_reg<4>" BEL 
"synthesizer_interface/synth/shift_reg_reg<19>" BEL 
"audio_interface/aud/data_sreg_reg<0>" BEL "bootstrap/wr_source/r00/q_reg<0>" 
BEL "synthesizer_interface/synth/clock_reg<3>" BEL 
"bootstrap/wr_source/r12/q_reg<1>" BEL "audio_interface/aud/ser_stb_reg" BEL 
"iic_bus_interface/iic/shift_reg_reg<0>" BEL "bootstrap/dma_cnt/iq_reg<3>" BEL 
"bootstrap/wr_source/r02/q_reg<0>" BEL "interrupt_source/q_reg<3>" BEL 
"interrupt_source/divide_reg<0>" BEL "bootstrap/wr_source/r10/q_reg<1>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<10>" BEL "bootstrap/tx/sreg_reg<0>" 
BEL "internal_port/sync/wr_n_latch_reg" BEL 
"tod_receiver/tod_receiver/manchester_decoder/edge_n_reg" BEL 
"synthesizer_interface/synth/shift_reg_reg<21>" BEL 
"antenna_interface/ant/shift_reg_reg<1>" BEL "audio_interface/aud/cycle_reg<3>" 
BEL "tod_receiver/tod_receiver/manchester_decoder/timeout_reg<3>" BEL 
"fan_interface/pwm/shift_reg_reg<8>" BEL 
"synthesizer_interface/synth/cycle_reg<4>" BEL "audio_interface/aud/busy_reg" 
BEL "bootstrap/rx/sreg_reg<7>" BEL "rtc_divide/clock_reg<6>" BEL 
"internal_port/sync/ale_select_reg" BEL "audio_interface/aud/comm_sreg_reg<4>" 
BEL "tod_receiver/tod_receiver/shift_reg_reg<7>" BEL 
"iic_bus_interface/iic/cycle_reg<0>" BEL 
"synthesizer_interface/sync_high/wr_n_latch_reg" BEL 
"iic_bus_interface/iic/clock_reg<4>" BEL "bootstrap/tx/baud_reg<8>" BEL 
"fill_output/fill_cc_dat_reg" BEL "audio_interface/aud/clock_reg<2>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/sdai_1_reg" BEL 
"synthesizer_interface/synth/shift_reg_reg<3>" BEL 
"audio_interface/aud/data_sreg_reg<1>" BEL "audio_interface/aud/free_clk_reg" 
BEL "receiver_interface/dac/shift_reg_reg<9>" BEL 
"bootstrap/wr_source/r00/q_reg<1>" BEL "fan_interface/sync/ale_latch_reg" BEL 
"bootstrap/wr_source/r12/q_reg<0>" BEL 
"synthesizer_interface/synth/clock_reg<2>" BEL "bootstrap/dma_cnt/iq_reg<2>" 
BEL "bootstrap/wr_source/r02/q_reg<1>" BEL "interrupt_source/q_reg<4>" BEL 
"bootstrap/wr_source/r10/q_reg<0>" BEL "bootstrap/tx/sreg_reg<1>" BEL 
"memory_interface/dff_reg" BEL "fan_interface/pwm/shift_reg_reg<10>" BEL 
"synthesizer_interface/synth/shift_reg_reg<22>" BEL 
"antenna_interface/ant/shift_reg_reg<2>" BEL "audio_interface/aud/cycle_reg<4>" 
BEL "tod_receiver/tod_receiver/manchester_decoder/timeout_reg<2>" BEL 
"fan_interface/pwm/shift_reg_reg<7>" BEL 
"receiver_interface/sync/wr_n_latch_reg" BEL "bootstrap/rx/busy_reg" BEL 
"synthesizer_interface/synth/cycle_reg<3>" BEL 
"synthesizer_interface/synth/ser_enbl_reg<0>" BEL "rtc_divide/clock_reg<7>" BEL 
"iic_bus_interface/iic/scl_reg" BEL "audio_interface/aud/comm_sreg_reg<3>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<6>" BEL 
"iic_bus_interface/iic/cycle_reg<1>" BEL "iic_bus_interface/iic/clock_reg<3>" 
BEL "bootstrap/tx/baud_reg<9>" BEL "audio_interface/aud/clock_reg<3>" BEL 
"synthesizer_interface/synth/shift_reg_reg<2>" BEL 
"audio_interface/aud/data_sreg_reg<2>" BEL 
"receiver_interface/dac/shift_reg_reg<8>" BEL "bootstrap/wr_source/r00/q_reg<2>"
 BEL "synthesizer_interface/synth/clock_reg<1>" BEL 
"bootstrap/dma_cnt/iq_reg<1>" BEL "bootstrap/wr_source/r02/q_reg<2>" BEL 
"fan_interface/pwm/clock_reg<0>" BEL "interrupt_source/q_reg<5>" BEL 
"bootstrap/tx/sreg_reg<2>" BEL "bootstrap/rx/baud16_reg<6>" BEL 
"fan_interface/pwm/shift_reg_reg<11>" BEL 
"synthesizer_interface/synth/shift_reg_reg<23>" BEL 
"antenna_interface/ant/shift_reg_reg<3>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<1>" BEL 
"fan_interface/pwm/shift_reg_reg<6>" BEL 
"synthesizer_interface/synth/cycle_reg<2>" BEL 
"synthesizer_interface/synth/ser_enbl_reg<1>" BEL "rtc_divide/clock_reg<8>" BEL 
"audio_interface/aud/comm_sreg_reg<2>" BEL "bootstrap/tx/int_busy_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<5>" BEL 
"iic_bus_interface/iic/cycle_reg<2>" BEL "iic_bus_interface/iic/clock_reg<2>" 
BEL "audio_interface/aud/clock_reg<4>" BEL 
"synthesizer_interface/synth/shift_reg_reg<1>" BEL 
"audio_interface/aud/data_sreg_reg<3>" BEL "tod_receiver/tod_receiver/dinv_reg" 
BEL "bootstrap/wr_source/r20/q_reg<0>" BEL "bootstrap/wr_source/r23/q_reg<3>" 
BEL "receiver_interface/dac/shift_reg_reg<7>" BEL 
"bootstrap/wr_source/r00/q_reg<3>" BEL "bootstrap/dma_cnt/iq_reg<10>" BEL 
"synthesizer_interface/synth/clock_reg<0>" BEL 
"receiver_interface/dac/ser_ld_n_reg" BEL "bootstrap/wr_source/r22/q_reg<0>" 
BEL "bootstrap/wr_source/r21/q_reg<3>" BEL "bootstrap/dma_cnt/iq_reg<0>" BEL 
"bootstrap/wr_source/r02/q_reg<3>" BEL "bootstrap/rd_control/tx_strt_reg" BEL 
"fan_interface/pwm/clock_reg<1>" BEL "bootstrap/tx/sreg_reg<3>" BEL 
"bootstrap/rx/baud16_reg<5>" BEL "fan_interface/pwm/shift_reg_reg<12>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/stb_reg" BEL 
"antenna_interface/ant/shift_reg_reg<4>" BEL "bootstrap/rd_control/cycle_reg<3>"
 BEL "tod_receiver/tod_receiver/manchester_decoder/timeout_reg<0>" BEL 
"bootstrap/rx/div16_reg<0>" BEL "fan_interface/pwm/shift_reg_reg<5>" BEL 
"iic_bus_interface/iic/stop_cycle_reg" BEL "antenna_interface/ant/clock_reg<8>" 
BEL "synthesizer_interface/synth/cycle_reg<1>" BEL 
"synthesizer_interface/synth/ser_enbl_reg<2>" BEL "rtc_divide/clock_reg<9>" BEL 
"audio_interface/aud/comm_sreg_reg<1>" BEL 
"synthesizer_interface/sync_low/ale_latch_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<4>" BEL 
"iic_bus_interface/iic/cycle_reg<3>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/sel_fall_reg" BEL 
"synthesizer_interface/synth/shift_reg_reg<10>" BEL 
"iic_bus_interface/iic/clock_reg<1>" BEL "audio_interface/sync/ale_select_reg" 
BEL "synthesizer_interface/synth/shift_reg_reg<0>" BEL 
"audio_interface/aud/data_sreg_reg<4>" BEL "bootstrap/wr_source/r20/q_reg<1>" 
BEL "bootstrap/wr_source/r23/q_reg<2>" BEL 
"iic_bus_interface/iic/shift_reg_reg<9>" BEL 
"receiver_interface/dac/shift_reg_reg<6>" BEL "fill_output/sync/ale_select_reg" 
BEL "bootstrap/dma_cnt/iq_reg<11>" BEL "bootstrap/decode/ext_reg<1>" BEL 
"bootstrap/wr_source/r22/q_reg<1>" BEL "bootstrap/wr_source/r21/q_reg<2>" BEL 
"tod_receiver/sync/ale_latch_reg" BEL "antenna_interface/ant/int_busy_reg" BEL 
"fan_interface/pwm/clock_reg<2>" BEL "bootstrap/tx/sreg_reg<4>" BEL 
"bootstrap/rx/baud16_reg<4>" BEL "receiver_interface/sync/ale_latch_reg" BEL 
"external_port/sync/wr_n_latch_reg" BEL "fan_interface/pwm/shift_reg_reg<13>" 
BEL "receiver_interface/dac/clock_reg<0>" BEL 
"antenna_interface/ant/shift_reg_reg<5>" BEL "bootstrap/rd_control/cycle_reg<2>"
 BEL "bootstrap/rx/div16_reg<1>" BEL "fan_interface/pwm/shift_reg_reg<4>" BEL 
"tod_receiver/sync/ale_select_reg" BEL "iic_bus_interface/sync/ale_latch_reg" 
BEL "tod_receiver/tod_receiver/manchester_decoder/sdai_2_reg" BEL 
"antenna_interface/ant/clock_reg<7>" BEL 
"synthesizer_interface/synth/cycle_reg<0>" BEL 
"audio_interface/aud/comm_sreg_reg<0>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<3>" BEL 
"synthesizer_interface/synth/shift_reg_reg<11>" BEL 
"synthesizer_interface/sync_low/ale_select_reg" BEL 
"iic_bus_interface/iic/clock_reg<0>" BEL 
"antenna_interface/ant/shift_reg_reg<10>" BEL 
"audio_interface/aud/data_sreg_reg<5>" BEL "bootstrap/wr_source/r20/q_reg<2>" 
BEL "bootstrap/wr_source/r23/q_reg<1>" BEL 
"iic_bus_interface/iic/shift_reg_reg<8>" BEL "bootstrap/wr_control/cycle_reg<2>"
 BEL "receiver_interface/dac/shift_reg_reg<5>" BEL 
"bootstrap/dma_cnt/iq_reg<12>" BEL "bootstrap/decode/ext_reg<0>" BEL 
"bootstrap/wr_source/r22/q_reg<2>" BEL "tod_receiver/tod_receiver/cycle_reg<3>" 
BEL "bootstrap/wr_source/r21/q_reg<1>" BEL "fan_interface/pwm/clock_reg<3>" BEL 
"bootstrap/tx/sreg_reg<5>" BEL "bootstrap/rx/baud16_reg<3>" BEL 
"fan_interface/pwm/shift_reg_reg<14>" BEL "receiver_interface/dac/cycle_reg<3>" 
BEL "receiver_interface/dac/clock_reg<1>" BEL "external_port/sync/ale_latch_reg"
 BEL "antenna_interface/ant/shift_reg_reg<6>" BEL 
"audio_interface/sync/wren_reg" BEL "bootstrap/rd_control/cycle_reg<1>" BEL 
"bootstrap/rx/div16_reg<2>" BEL "fan_interface/pwm/shift_reg_reg<3>" BEL 
"antenna_interface/ant/clock_reg<6>" BEL "iic_bus_interface/iic/busy_reg" BEL 
"bootstrap/tx/baud_reg<0>" BEL "antenna_interface/sync/wr_n_latch_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<2>" BEL 
"synthesizer_interface/synth/shift_reg_reg<12>" BEL 
"receiver_interface/dac/shift_reg_reg<10>" BEL 
"antenna_interface/ant/shift_reg_reg<11>" BEL "internal_port/sync/wren_reg" BEL 
"bootstrap/wr_source/r03/q_reg<3>" BEL "audio_interface/aud/data_sreg_reg<6>" 
BEL "bootstrap/wr_source/r20/q_reg<3>" BEL "bootstrap/wr_source/r23/q_reg<0>" 
BEL "iic_bus_interface/iic/shift_reg_reg<7>" BEL "fill_output/fill_req_reg" BEL 
"bootstrap/wr_control/cycle_reg<1>" BEL 
"receiver_interface/dac/shift_reg_reg<4>" BEL 
"receiver_interface/dac/ser_clk_reg" BEL "bootstrap/wr_source/r01/q_reg<3>" BEL 
"bootstrap/dma_cnt/iq_reg<13>" BEL "bootstrap/wr_source/r22/q_reg<3>" BEL 
"bootstrap/wr_source/r21/q_reg<0>" BEL "tod_receiver/tod_receiver/cycle_reg<2>" 
BEL "fan_interface/pwm/clock_reg<4>" BEL "bootstrap/tx/sreg_reg<6>" BEL 
"iic_bus_interface/iic/shift_reg_reg<10>" BEL 
"fan_interface/sync/wr_n_latch_reg" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<13>" BEL 
"bootstrap/rx/baud16_reg<2>" BEL "external_port/rcp_reg1_reg<AM_MODE_IND>" BEL 
"fan_interface/pwm/shift_reg_reg<15>" BEL "receiver_interface/dac/cycle_reg<2>" 
BEL "receiver_interface/dac/clock_reg<2>" BEL 
"antenna_interface/ant/shift_reg_reg<7>" BEL "bootstrap/rx/sreg_reg<0>" BEL 
"bootstrap/rd_control/cycle_reg<0>" BEL "bootstrap/rx/div16_reg<3>" BEL 
"fan_interface/pwm/shift_reg_reg<2>" BEL "external_port/sync/wren_reg" BEL 
"antenna_interface/ant/clock_reg<5>" BEL "bootstrap/rx/int_stb_reg" BEL 
"bootstrap/tx/baud_reg<1>" BEL "bootstrap/incr_en_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<1>" BEL 
"synthesizer_interface/synth/shift_reg_reg<13>" BEL 
"receiver_interface/dac/shift_reg_reg<11>" BEL 
"receiver_interface/sync/wren_reg" BEL "antenna_interface/ant/shift_reg_reg<12>"
 BEL "bootstrap/wr_source/r03/q_reg<2>" BEL "antenna_interface/ant/cycle_reg<0>"
 BEL "audio_interface/aud/data_sreg_reg<7>" BEL 
"iic_bus_interface/iic/shift_reg_reg<6>" BEL "bootstrap/dma_cnt/iq_reg<9>" BEL 
"bootstrap/wr_control/cycle_reg<0>" BEL 
"receiver_interface/dac/shift_reg_reg<3>" BEL "bootstrap/wr_source/r01/q_reg<2>"
 BEL "bootstrap/dma_cnt/iq_reg<14>" BEL "tod_receiver/tod_receiver/cycle_reg<1>"
 BEL "fan_interface/pwm/clock_reg<5>" BEL "fill_output/sync/wren_reg" BEL 
"bootstrap/tx/sreg_reg<7>" BEL "iic_bus_interface/iic/shift_reg_reg<11>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<12>" BEL 
"bootstrap/rx/baud16_reg<1>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<9>" BEL 
"fan_interface/pwm/shift_reg_reg<16>" BEL "receiver_interface/dac/cycle_reg<1>" 
BEL "receiver_interface/dac/clock_reg<3>" BEL 
"audio_interface/aud/ser_doe_n_reg" BEL "antenna_interface/ant/shift_reg_reg<8>"
 BEL "iic_bus_interface/sync/wr_n_latch_reg" BEL "bootstrap/rx/sreg_reg<1>" BEL 
"synthesizer_interface/sync_high/ale_select_reg" BEL 
"fan_interface/sync/ale_select_reg" BEL "rtc_divide/clock_reg<0>" BEL 
"fan_interface/pwm/shift_reg_reg<1>" BEL "bootstrap/decode/int_active_reg" BEL 
"antenna_interface/ant/clock_reg<4>" BEL 
"synthesizer_interface/sync_high/ale_latch_reg" BEL 
"bootstrap/wr_control/cycle_rst_n_reg" BEL "interrupt_source/intr_reg" BEL 
"iic_bus_interface/sync/wren_reg" BEL "bootstrap/tx/baud_reg<2>" BEL 
"antenna_interface/sync/ale_latch_reg" BEL "tod_receiver/sync/wren_reg" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<0>" BEL 
"synthesizer_interface/synth/shift_reg_reg<9>" BEL 
"synthesizer_interface/synth/shift_reg_reg<14>" BEL 
"receiver_interface/dac/shift_reg_reg<12>" BEL 
"antenna_interface/ant/shift_reg_reg<13>" BEL "receiver_interface/dac/busy_reg" 
BEL "bootstrap/wr_source/r03/q_reg<1>" BEL "antenna_interface/ant/cycle_reg<1>" 
BEL "iic_bus_interface/iic/shift_reg_reg<5>" BEL "bootstrap/dma_cnt/iq_reg<8>" 
BEL "bootstrap/wr_source/r11/q_reg<0>" BEL 
"receiver_interface/dac/shift_reg_reg<2>" BEL 
"internal_port/rcp_reg2_reg<BAND_SEL_1>" BEL "bootstrap/wr_source/r01/q_reg<1>" 
BEL "bootstrap/dma_cnt/iq_reg<15>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<15>" BEL "bootstrap/rx/cycle_reg<3>" 
BEL "fill_output/fill_clk_reg" BEL "receiver_interface/sync/ale_select_reg" BEL 
"tod_receiver/tod_receiver/cycle_reg<0>" BEL "bootstrap/wr_source/r13/q_reg<0>" 
BEL "fan_interface/pwm/clock_reg<6>" BEL "bootstrap/tx/sreg_reg<8>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<11>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<8>" BEL 
"bootstrap/rx/baud16_reg<0>" BEL "bootstrap/wr_control/wr_n_reg" BEL 
"fan_interface/pwm/shift_reg_reg<17>" BEL "receiver_interface/dac/cycle_reg<0>" 
BEL "antenna_interface/ant/shift_reg_reg<9>" BEL "bootstrap/tx/cycle_reg<0>" 
BEL "bootstrap/rx/sreg_reg<2>" BEL "rtc_divide/clock_reg<1>" BEL 
"fan_interface/pwm/shift_reg_reg<0>" BEL "antenna_interface/ant/clock_reg<3>" 
BEL "synthesizer_interface/synth/int_busy_reg" BEL "bootstrap/tx/baud_reg<3>" 
BEL "synthesizer_interface/synth/shift_reg_reg<8>" BEL 
"synthesizer_interface/synth/shift_reg_reg<15>" BEL 
"antenna_interface/ant/shift_reg_reg<14>" BEL 
"audio_interface/aud/read_cycle_reg" BEL "bootstrap/wr_source/r03/q_reg<0>" BEL 
"antenna_interface/ant/cycle_reg<2>" BEL 
"iic_bus_interface/iic/shift_reg_reg<4>" BEL "bootstrap/dma_cnt/iq_reg<7>" BEL 
"bootstrap/wr_source/r11/q_reg<1>" BEL "rtc_divide/clk_reg" BEL 
"receiver_interface/dac/shift_reg_reg<1>" BEL 
"internal_port/rcp_reg2_reg<BAND_SEL_0>" BEL "bootstrap/wr_source/r01/q_reg<0>" 
BEL "bootstrap/dma_cnt/iq_reg<16>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<14>" BEL "bootstrap/rx/cycle_reg<2>" 
BEL "bootstrap/wr_source/r13/q_reg<1>" BEL 
"iic_bus_interface/iic/read_cycle_reg" BEL "fan_interface/pwm/clock_reg<7>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<10>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<7>" BEL 
"audio_interface/sync/ale_latch_reg" BEL "bootstrap/tx/cycle_reg<1>" BEL 
"bootstrap/rx/sreg_reg<3>" BEL "rtc_divide/clock_reg<2>" BEL 
"fan_interface/sync/wren_reg" BEL 
"tod_receiver/tod_receiver/manchester_decoder/to_dff_reg" BEL 
"antenna_interface/ant/clock_reg<2>" BEL "bootstrap/tx/baud_reg<4>" BEL 
"synthesizer_interface/synth/shift_reg_reg<7>" BEL 
"synthesizer_interface/synth/shift_reg_reg<16>" BEL 
"antenna_interface/ant/shift_reg_reg<15>" BEL "antenna_interface/sync/wren_reg" 
BEL "antenna_interface/ant/cycle_reg<3>" BEL 
"iic_bus_interface/iic/shift_reg_reg<3>" BEL "bootstrap/dma_cnt/iq_reg<6>" BEL 
"bootstrap/wr_source/r11/q_reg<2>" BEL "receiver_interface/dac/shift_reg_reg<0>"
 BEL "iic_bus_interface/sync/ale_select_reg" BEL "bootstrap/dma_cnt/iq_reg<17>" 
BEL "interrupt_source/q_reg<0>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<13>" BEL "bootstrap/rx/cycle_reg<1>" 
BEL "tod_receiver/tod_receiver/active_reg" BEL 
"audio_interface/sync/wr_n_latch_reg" BEL "bootstrap/wr_source/r13/q_reg<2>" 
BEL "fan_interface/pwm/clock_reg<8>" BEL "audio_interface/aud/cycle_reg<0>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<6>" BEL 
"tod_receiver/tod_en_reg" BEL "receiver_interface/dac/ser_dato_reg" BEL 
"bootstrap/tx/cycle_reg<2>" BEL "bootstrap/rx/sreg_reg<4>" BEL 
"rtc_divide/clock_reg<3>" BEL "external_port/rcp_reg1_reg<ADF_HOME_EN>" BEL 
"audio_interface/aud/comm_sreg_reg<7>" BEL "antenna_interface/ant/clock_reg<1>" 
BEL "iic_bus_interface/iic/sda_oe_n_reg" BEL "fill_output/sync/wr_n_latch_reg" 
BEL "antenna_interface/ant/ser_clk_reg" BEL "iic_bus_interface/iic/clock_reg<7>"
 BEL "bootstrap/tx/baud_reg<5>" BEL "tod_receiver/sync/wr_n_latch_reg" BEL 
"synthesizer_interface/synth/shift_reg_reg<6>" BEL 
"synthesizer_interface/synth/shift_reg_reg<17>" BEL 
"fan_interface/pwm/clock_reg<10>" BEL "synthesizer_interface/sync_low/wren_reg" 
BEL "antenna_interface/ant/cycle_reg<4>" BEL "external_port/sync/ale_select_reg"
 BEL "bootstrap/wr_source/r12/q_reg<3>" BEL 
"iic_bus_interface/iic/shift_reg_reg<2>" BEL "bootstrap/dma_cnt/iq_reg<5>" BEL 
"bootstrap/wr_source/r11/q_reg<3>" BEL 
"synthesizer_interface/sync_low/wr_n_latch_reg" BEL 
"bootstrap/dma_cnt/iq_reg<18>" BEL "interrupt_source/q_reg<1>" BEL 
"bootstrap/wr_source/r10/q_reg<3>" BEL 
"tod_receiver/tod_receiver/shift_reg_reg<12>" BEL "bootstrap/rx/cycle_reg<0>" 
BEL "bootstrap/wr_source/r13/q_reg<3>" BEL "fan_interface/pwm/clock_reg<9>" BEL 
"tod_receiver/tod_receiver/stb_reg" BEL "bootstrap/rd_control/cyc_rst_n_reg" 
BEL "audio_interface/aud/cycle_reg<1>" BEL 
"external_port/rcp_reg1_reg<SC_FH_IND>" BEL 
"tod_receiver/tod_receiver/manchester_decoder/timeout_reg<5>" BEL 
"bootstrap/tx/baud_reg<10>" BEL "internal_port/sync/ale_latch_reg" BEL 
"bootstrap/tx/cycle_reg<3>" BEL "bootstrap/rx/sreg_reg<5>" BEL 
"rtc_divide/clock_reg<4>" BEL "external_port/rcp_reg1_reg<SQUELCH_IND>" BEL 
"audio_interface/aud/comm_sreg_reg<6>" BEL "antenna_interface/ant/clock_reg<0>" 
BEL "tod_receiver/tod_receiver/shift_reg_reg<9>" BEL 
"antenna_interface/sync/ale_select_reg" BEL "iic_bus_interface/iic/clock_reg<6>"
 BEL "bootstrap/tx/baud_reg<6>" BEL "audio_interface/aud/clock_reg<0>" BEL 
"synthesizer_interface/synth/shift_reg_reg<5>" BEL 
"synthesizer_interface/synth/shift_reg_reg<18>" BEL 
"fill_output/sync/ale_latch_reg" BEL "fan_interface/pwm/clock_reg<11>" BEL 
"synthesizer_interface/synth/clock_reg<4>" BEL 
"bootstrap/wr_source/r12/q_reg<2>" BEL "iic_bus_interface/iic/shift_reg_reg<1>" 
BEL "bootstrap/dma_cnt/iq_reg<4>" BEL 
"external_port/rcp_reg1_reg<BIT_FAULT_DSC>" ;
TS_01 = PERIOD TIMEGRP "clk"  20 nS   HIGH 50.000 % ;
SCHEMATIC END ;