ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd ngdbuild: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd Launcher: "bdes.ngo" is up to date. Reading NGO file "C:/davin/1097/englabs/bdes2/xproj/ver1_proto/bdes.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "C:/davin/1097/englabs/bdes2/bdes.ucf" ... Checking timing specifications ... Checking expanded design ... WARNING:basnu:147 - clock net "address_generator/n31<0>" has non-clock connections WARNING:basnu:148 - clock net "address_generator/n31<0>" drives no clock pins NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 2 Writing NGD file "bdes.ngd" ... Writing NGDBUILD log file "bdes.bld"... NGDBUILD done. ================================================== map -p xc4010xl-1-pq208 -o map.ncd bdes.ngd bdes.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "bdes.ngd"... Using target part "4010xlpq208-1". MAP xc4000xl directives: Partname = "xc4010xl-1-pq208". Covermode = "area". Pack CLBs to 100%. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 2 Number of CLBs: 350 out of 400 87% CLB Flip Flops: 441 CLB Latches: 0 4 input LUTs: 657 (41 used as route-throughs) 3 input LUTs: 153 (36 used as route-throughs) Number of bonded IOBs: 105 out of 160 65% IOB Flops: 0 IOB Latches: 0 Number of clock IOB pads: 2 out of 12 16% Number of BUFGLSs: 2 out of 8 25% Total equivalent gate count for design: 6868 Additional JTAG gate count for IOBs: 5040 Writing design file "map.ncd"... Removed Logic Summary: Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -i 4 -d 0 map.ncd bdes.ncd bdes.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 10 secs Finished initial Timing Analysis. REAL time: 14 secs Starting initial Placement phase. REAL time: 17 secs Finished initial Placement phase. REAL time: 17 secs Starting Constructive Placer. REAL time: 18 secs Placer score = 650717 Placer score = 540365 Placer score = 525783 Placer score = 477412 Placer score = 445208 Placer score = 437080 Placer score = 399221 Placer score = 390204 Placer score = 367060 Placer score = 349572 Placer score = 341857 Placer score = 328474 Placer score = 296327 Placer score = 286231 Placer score = 283095 Placer score = 267469 Placer score = 253539 Placer score = 246123 Placer score = 233354 Placer score = 228723 Placer score = 222112 Placer score = 219504 Placer score = 212084 Placer score = 206372 Placer score = 201960 Placer score = 198339 Placer score = 196680 Placer score = 196575 Placer score = 194986 Placer score = 193978 Placer score = 193760 Placer score = 191793 Placer score = 191226 Placer score = 190103 Placer score = 189460 Placer score = 189190 Placer score = 188800 Finished Constructive Placer. REAL time: 8 mins Writing design to file "bdes.ncd". Starting Optimizing Placer. REAL time: 8 mins 1 secs Optimizing .. Swapped 30 comps. Xilinx Placer [1] 188174 REAL time: 8 mins 34 secs Finished Optimizing Placer. REAL time: 8 mins 34 secs Writing design to file "bdes.ncd". Total REAL time to Placer completion: 8 mins 35 secs Total CPU time to Placer completion: 8 mins 27 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 8 mins 55 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1458062) REAL time: 9 mins 36 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (52986) REAL time: 11 mins WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (18826) REAL time: 13 mins 37 secs End of iteration 4 3402 successful; 0 unrouted; (15766) REAL time: 15 mins 47 secs Writing design to file "bdes.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (15593) REAL time: 17 mins 37 secs Writing design to file "bdes.ncd". Total REAL time: 17 mins 38 secs Total CPU time: 17 mins 28 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 41 secs Total CPU time to Router completion: 17 mins 31 secs Generating PAR statistics. Timing Score: 15593 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 25.789ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "bdes.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 52 secs Total CPU time to PAR completion: 17 mins 41 secs PAR done. ================================================== trce bdes.ncd -a -v 3 -o bdes.twr Loading device database for application trce from file "bdes.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application trce from file '4010xl.nph' in environment C:/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.21 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: bdes.ncd Physical constraint file: bdes.pcf Device,speed: xc4010xl,-1 (x1_0.37 1.22 FINAL) Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 10 Score: 15593 Constraints cover 7720 paths, 0 nets, and 2846 connections (83.7% coverage) Design statistics: Minimum period: 25.789ns (Maximum frequency: 38.776MHz) Analysis completed Tue Oct 06 09:24:53 1998 -------------------------------------------------------------------------------- Total time: 19 secs ================================================== par -w -ol 1 -i 4 -d 0 map.ncd bdes.ncd bdes.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 11 secs Finished initial Timing Analysis. REAL time: 15 secs Starting initial Placement phase. REAL time: 18 secs Finished initial Placement phase. REAL time: 18 secs Starting Constructive Placer. REAL time: 19 secs Placer score = 778397 Placer score = 555523 Placer score = 524465 Placer score = 438402 Placer score = 385322 Placer score = 368122 Placer score = 324895 Placer score = 314068 Placer score = 292081 Placer score = 272769 Placer score = 264131 Placer score = 252924 Placer score = 241920 Placer score = 241558 Placer score = 235878 Placer score = 233853 Placer score = 230058 Placer score = 228971 Placer score = 226871 Placer score = 225910 Finished Constructive Placer. REAL time: 2 mins 56 secs Writing design to file "bdes.ncd". Total REAL time to Placer completion: 2 mins 58 secs Total CPU time to Placer completion: 2 mins 56 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 3 mins 18 secs Starting iterative routing. Routing active signals. End of iteration 1 3343 successful; 59 unrouted; (5264597) REAL time: 7 mins 42 secs End of iteration 2 3401 successful; 1 unrouted; (3488756) REAL time: 10 mins 16 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. End of iteration 3 3402 successful; 0 unrouted; (323663) REAL time: 12 mins 26 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 4 3402 successful; 0 unrouted; (208121) REAL time: 15 mins 10 secs Writing design to file "bdes.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (207682) REAL time: 16 mins 52 secs Writing design to file "bdes.ncd". Total REAL time: 16 mins 53 secs Total CPU time: 16 mins 36 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 16 mins 57 secs Total CPU time to Router completion: 16 mins 39 secs Generating PAR statistics. Timing Score: 207682 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 29.716ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "bdes.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 9 secs Total CPU time to PAR completion: 16 mins 49 secs PAR done. ================================================== trce bdes.ncd -a -v 3 -o bdes.twr Loading device database for application trce from file "bdes.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application trce from file '4010xl.nph' in environment C:/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.21 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: bdes.ncd Physical constraint file: bdes.pcf Device,speed: xc4010xl,-1 (x1_0.37 1.22 FINAL) Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 101 Score: 207682 Constraints cover 7720 paths, 0 nets, and 2846 connections (83.7% coverage) Design statistics: Minimum period: 29.716ns (Maximum frequency: 33.652MHz) Analysis completed Tue Oct 06 14:19:38 1998 -------------------------------------------------------------------------------- Total time: 18 secs