PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Mon Oct 05 13:03:03 1998 par -w -ol 4 -i 4 -d 0 map.ncd bdes.ncd bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 15 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 16 secs Placer score = 515707 Placer score = 367949 Placer score = 351842 Placer score = 329546 Placer score = 307925 Placer score = 288077 Placer score = 274053 Placer score = 270058 Placer score = 258410 Placer score = 233543 Placer score = 220206 Placer score = 204469 Placer score = 195889 Placer score = 195408 Placer score = 184274 Placer score = 180155 Placer score = 176831 Placer score = 173110 Placer score = 162135 Placer score = 162002 Placer score = 156144 Placer score = 153681 Placer score = 153351 Placer score = 150960 Placer score = 148650 Placer score = 146340 Placer score = 143610 Placer score = 141690 Placer score = 141390 Placer score = 140580 Placer score = 139890 Placer score = 139470 Placer score = 139440 Finished Constructive Placer. REAL time: 8 mins 29 secs Writing design to file "bdes.ncd". Starting Optimizing Placer. REAL time: 8 mins 29 secs Optimizing .. Swapped 12 comps. Xilinx Placer [1] 139170 REAL time: 9 mins Optimizing .. Swapped 2 comps. Xilinx Placer [2] 139170 REAL time: 9 mins 29 secs Finished Optimizing Placer. REAL time: 9 mins 29 secs Writing design to file "bdes.ncd". Total REAL time to Placer completion: 9 mins 30 secs Total CPU time to Placer completion: 9 mins 24 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 45 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (837616) REAL time: 10 mins 15 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (0) REAL time: 10 mins 48 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "bdes.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (0) REAL time: 12 mins 12 secs Writing design to file "bdes.ncd". Total REAL time: 12 mins 13 secs Total CPU time: 12 mins 6 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. Total REAL time to Router completion: 12 mins 16 secs Total CPU time to Router completion: 12 mins 9 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 700 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.120 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.158 ns The Maximum Pin Delay is: 21.088 ns The Average Connection Delay on the 10 Worst Nets is: 14.404 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3273 128 1 0 0 0 Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- TS_01 = PERIOD TIMEGRP "clk" 30 nS HIG | 30.000ns | 27.941ns | 5 H 50.000 % | | | -------------------------------------------------------------------------------- All constraints were met. Writing design to file "bdes.ncd". All signals are completely routed. Total REAL time to PAR completion: 12 mins 25 secs Total CPU time to PAR completion: 12 mins 18 secs PAR done.