ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd ngdbuild: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd Launcher: "bdes.ngo" is up to date. Reading NGO file "C:/davin/1097/englabs/bdes2/xproj/ver2/bdes.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "C:/davin/1097/englabs/bdes2/bdes.ucf" ... Checking timing specifications ... Checking expanded design ... WARNING:basnu:147 - clock net "address_generator/n31<0>" has non-clock connections WARNING:basnu:148 - clock net "address_generator/n31<0>" drives no clock pins NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 2 Writing NGD file "bdes.ngd" ... Writing NGDBUILD log file "bdes.bld"... NGDBUILD done. ================================================== map -p xc4010xl-1-pq208 -o map.ncd bdes.ngd bdes.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "bdes.ngd"... Using target part "4010xlpq208-1". MAP xc4000xl directives: Partname = "xc4010xl-1-pq208". Covermode = "area". Pack CLBs to 100%. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 2 Number of CLBs: 350 out of 400 87% CLB Flip Flops: 441 CLB Latches: 0 4 input LUTs: 657 (41 used as route-throughs) 3 input LUTs: 153 (36 used as route-throughs) Number of bonded IOBs: 105 out of 160 65% IOB Flops: 0 IOB Latches: 0 Number of clock IOB pads: 2 out of 12 16% Number of BUFGLSs: 2 out of 8 25% Total equivalent gate count for design: 6868 Additional JTAG gate count for IOBs: 5040 Writing design file "map.ncd"... Removed Logic Summary: Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 4 -i 4 -d 0 map.ncd bdes.ncd bdes.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 15 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 16 secs Placer score = 515707 Placer score = 367949 Placer score = 351842 Placer score = 329546 Placer score = 307925 Placer score = 288077 Placer score = 274053 Placer score = 270058 Placer score = 258410 Placer score = 233543 Placer score = 220206 Placer score = 204469 Placer score = 195889 Placer score = 195408 Placer score = 184274 Placer score = 180155 Placer score = 176831 Placer score = 173110 Placer score = 162135 Placer score = 162002 Placer score = 156144 Placer score = 153681 Placer score = 153351 Placer score = 150960 Placer score = 148650 Placer score = 146340 Placer score = 143610 Placer score = 141690 Placer score = 141390 Placer score = 140580 Placer score = 139890 Placer score = 139470 Placer score = 139440 Finished Constructive Placer. REAL time: 8 mins 29 secs Writing design to file "bdes.ncd". Starting Optimizing Placer. REAL time: 8 mins 29 secs Optimizing .. Swapped 12 comps. Xilinx Placer [1] 139170 REAL time: 9 mins Optimizing .. Swapped 2 comps. Xilinx Placer [2] 139170 REAL time: 9 mins 29 secs Finished Optimizing Placer. REAL time: 9 mins 29 secs Writing design to file "bdes.ncd". Total REAL time to Placer completion: 9 mins 30 secs Total CPU time to Placer completion: 9 mins 24 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 45 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (837616) REAL time: 10 mins 15 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (0) REAL time: 10 mins 48 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "bdes.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (0) REAL time: 12 mins 12 secs Writing design to file "bdes.ncd". Total REAL time: 12 mins 13 secs Total CPU time: 12 mins 6 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. Total REAL time to Router completion: 12 mins 16 secs Total CPU time to Router completion: 12 mins 9 secs Generating PAR statistics. Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- TS_01 = PERIOD TIMEGRP "clk" 30 nS HIG | 30.000ns | 27.941ns | 5 H 50.000 % | | | -------------------------------------------------------------------------------- All constraints were met. Writing design to file "bdes.ncd". All signals are completely routed. Total REAL time to PAR completion: 12 mins 25 secs Total CPU time to PAR completion: 12 mins 18 secs PAR done. ================================================== trce bdes.ncd -a -v 3 -o bdes.twr Loading device database for application trce from file "bdes.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application trce from file '4010xl.nph' in environment C:/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.21 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: bdes.ncd Physical constraint file: bdes.pcf Device,speed: xc4010xl,-1 (x1_0.37 1.22 FINAL) Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 7720 paths, 0 nets, and 2846 connections (83.7% coverage) Design statistics: Minimum period: 27.941ns (Maximum frequency: 35.790MHz) Analysis completed Mon Oct 05 13:15:45 1998 -------------------------------------------------------------------------------- Total time: 16 secs