ngdbuild -p xc4000xl C:\1097labs\epiclab\epiclab.edn xc4000xl.ngd
ngdbuild:  version M1.3.7
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc4000xl C:\1097labs\epiclab\epiclab.edn xc4000xl.ngd

Launcher: Using rule EDN_RULE
Launcher: epiclab.ngo being compiled because it does not exist
Launcher: Running edif2ngd from C:\1097labs\epiclab\xproj\ver1\
Launcher: Executing edif2ngd "C:\1097labs\epiclab\epiclab.edn" "epiclab.ngo"
edif2ngd:  version M1.3.7
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.
Writing the design to "epiclab.ngo"...
Launcher: "edif2ngd" exited with an exit code of 0.

Reading NGO file "C:/1097labs/epiclab/xproj/ver1/epiclab.ngo" ...
Reading component libraries for design expansion...

Running Timing Specification DRC...
Timing Specification DRC complete with no errors or warnings.

Running Logical Design DRC...
WARNING:basnu - logical net "$I2/CLR" has no driver
WARNING:basnu - logical net "$I2/D<0>" has no driver
WARNING:basnu - logical net "$I2/D<1>" has no driver
WARNING:basnu - logical net "$I2/D<2>" has no driver
WARNING:basnu - logical net "$I2/Q<0>" has no load
WARNING:basnu - logical net "$I2/Q<1>" has no load
WARNING:basnu - logical net "$I2/Q<2>" has no load
WARNING:basnu - logical net "$I23/CLR" has no driver
WARNING:basnu - logical net "$I1/CEO" has no load
WARNING:basnu - logical net "$I1/CLR" has no driver
Logical Design DRC complete with 10 warning(s).

NGDBUILD Design Results Summary:
  There were 10 Logical Design DRC warnings.
     51 total blocks expanded.
Writing NGD file "xc4000xl.ngd" ...

Writing NGDBUILD log file "xc4000xl.bld"...

NGDBUILD Done.

map -p xc4005xl-1-pc84 -o map.ncd ../xc4000xl.ngd epiclab.pcf
map:  version M1.3.7
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.
Reading NGD file "../xc4000xl.ngd"...
Using target part "4005xlpc84-1".
MAP xc4000xl directives:
   Partname="xc4005xl-1-pc84".
   No Guide File specified.
   No Guide Mode specified.
   Covermode="area".
   Coverlutsize=4.
   Coverfgsize=4.
   Perform logic replication.
   Pack CLBs to 100%.
Processing logical timing constraints...
Running general design DRC...
WARNING:basnu - logical net "$I2/CLR" has no driver
WARNING:basnu - logical net "$I2/D<0>" has no driver
WARNING:basnu - logical net "$I2/D<1>" has no driver
WARNING:basnu - logical net "$I2/D<2>" has no driver
WARNING:basnu - logical net "$I2/Q<0>" has no load
WARNING:basnu - logical net "$I2/Q<1>" has no load
WARNING:basnu - logical net "$I2/Q<2>" has no load
WARNING:basnu - logical net "$I23/CLR" has no driver
WARNING:basnu - logical net "$I1/CEO" has no load
WARNING:basnu - logical net "$I1/CLR" has no driver
Verifying F/HMAP validity based on pre-trimmed logic...
Removing unused logic...
Processing global clock buffers...
WARNING:baste:24 - All of the external outputs in this design are using
   slew-rate-limited output drivers.  The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the original
   design.  Please see your vendor interface documentation for specific
   information on how to do this within your design-entry tool.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I2/Q3' (output signal=ADDR<0>)
   	FDCE symbol `$I2/Q4' (output signal=ADDR<1>)
   	FDCE symbol `$I2/Q5' (output signal=ADDR<2>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I2/Q3' (output signal=ADDR<0>)
   	FDCE symbol `$I2/Q4' (output signal=ADDR<1>)
   	FDCE symbol `$I2/Q6' (output signal=ADDR<3>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I2/Q3' (output signal=ADDR<0>)
   	FDCE symbol `$I2/Q4' (output signal=ADDR<1>)
   	FDCE symbol `$I2/Q7' (output signal=ADDR<4>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I2/Q5' (output signal=ADDR<2>)
   	FDCE symbol `$I2/Q6' (output signal=ADDR<3>)
   	FDCE symbol `$I2/Q7' (output signal=ADDR<4>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>)
   	FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>)
   	FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>)
   	FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>)
   	FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>)
   	FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>)
   	FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>)
   	FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>)
   	FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>)
   	FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>)
   	FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>)
   	FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>)
   	FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
WARNING:x4kma:191 - The following symbols could not be constrained to a single
   CLB:
   	FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>)
   	FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>)
   	FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>)
   T  These symbols share the same BLKNM parameter value, which requires them to
   be mapped to the same CLB.
Optimizing...
WARNING:baste:164 - Components with same name COUNTER detected...uniquifying.
WARNING:baste:164 - Components with same name COUNTER detected...uniquifying.
WARNING:baste:164 - Components with same name COUNTER detected...uniquifying.
WARNING:baste:164 - Components with same name COUNTER_FD
   detected...uniquifying.
WARNING:baste:164 - Components with same name COUNTER_FD
   detected...uniquifying.
Removed Logic Summary:
   8 block(s) clipped
   2 block(s) removed
   3 block(s) optimized away
  14 signal(s) removed
   2 signal(s) merged

Design Summary:
   Number of warnings:    32
   Number of errors:       0
   Number of CLBs:             10 out of  196
      Flops/latches:     16
      4 input LUTs:      12
      3 input LUTs:      7
   Number of bonded IOBs:       5 out of   63
   Number of clock IOBs:        1 out of   12
   Number of BUFGLSs:           1 out of    8
Writing design file "map.ncd"...

par -w -l 4 -d 0 map.ncd epiclab.ncd epiclab.pcf
PAR: Xilinx Place And Route M1.3.7.
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.


Constraints file: epiclab.pcf

Placement level-cost: 4-1


Loading device database for application par from file "map.ncd".
   "ONECLOCK" is an NCD, version 2.27, device xc4005xl, package pc84, speed -1
Loading device for application par from file '4005xl.nph' in environment
C:/Xilinx.
Device speed data version:  x1_0.35.1.4 3.7ag PRELIMINARY.


Device utilization summary:

   IO            5/112     4% used
                 5/61      8% bonded
   LOGIC        10/196     5% used
   SPECIAL       1/1167    0% used

   CLKIOB        1/8      12% used
   IOB           4/112     3% used

   CLB          10/196     5% used

   BUFGLS        1/8      12% used


Starting initial Placement phase.  REAL time: 12 secs 
Finished initial Placement phase.  REAL time: 12 secs 

Starting Constructive Placer.  REAL time: 12 secs .
Placer score = 15780
Placer score = 13680
Placer score = 12780
Placer score = 12240
Placer score = 10080
Placer score = 8340
Placer score = 7740
Placer score = 6660
Placer score = 4140
Placer score = 3480
Placer score = 2700
Placer score = 2640
Finished Constructive Placer.  REAL time: 26 secs 

Dumping design to file "epiclab.ncd".

Starting Optimizing Placer.  REAL time: 26 secs 
Optimizing  
Swapped 3 comps.
Xilinx Placer [1]   2520   REAL time: 26 secs 
Finished Optimizing Placer.  REAL time: 26 secs 

Dumping design to file "epiclab.ncd".

Total REAL time to Placer completion: 26 secs 
Total CPU time to Placer completion: 26 secs 

0 connection(s) routed; 67 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 27 secs  
Starting iterative routing. 
End of iteration 1 
67 successful; 0 unrouted; (0) real time: 27 secs  
Constraints are met. 
Power and ground nets completely routed. 
Dumping design to file "epiclab.ncd".
Starting cleanup 
End of cleanup iteration 1 
67 successful; 0 unrouted; (0) real time: 28 secs  
Dumping design to file "epiclab.ncd".
Total CPU time 28 secs  
Total REAL time: 28 secs  
Completely routed. 
End of route.  67 routed (100.00%); 0 unrouted.
No errors found. 

Total REAL time to Router completion: 28 secs 
Total CPU time to Router completion: 28 secs 

Generating PAR statistics.
Timing Score: 0

Dumping design to file "epiclab.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 30 secs 
Total CPU time to PAR completion: 30 secs 

PAR done.