Xilinx Mapping Report File for Design "ONECLOCK" Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Section: DRC Messages ---------------------- WARNING:basnu - logical net "$I2/CLR" has no driver WARNING:basnu - logical net "$I2/D<0>" has no driver WARNING:basnu - logical net "$I2/D<1>" has no driver WARNING:basnu - logical net "$I2/D<2>" has no driver WARNING:basnu - logical net "$I2/Q<0>" has no load WARNING:basnu - logical net "$I2/Q<1>" has no load WARNING:basnu - logical net "$I2/Q<2>" has no load WARNING:basnu - logical net "$I23/CLR" has no driver WARNING:basnu - logical net "$I1/CEO" has no load WARNING:basnu - logical net "$I1/CLR" has no driver Section: Mapper Warnings and Errors ------------------------------------ WARNING:baste:24 - All of the external outputs in this design are using slew-rate-limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the original design. Please see your vendor interface documentation for specific information on how to do this within your design-entry tool. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I2/Q3' (output signal=ADDR<0>) FDCE symbol `$I2/Q4' (output signal=ADDR<1>) FDCE symbol `$I2/Q5' (output signal=ADDR<2>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I2/Q3' (output signal=ADDR<0>) FDCE symbol `$I2/Q4' (output signal=ADDR<1>) FDCE symbol `$I2/Q6' (output signal=ADDR<3>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I2/Q3' (output signal=ADDR<0>) FDCE symbol `$I2/Q4' (output signal=ADDR<1>) FDCE symbol `$I2/Q7' (output signal=ADDR<4>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I2/Q5' (output signal=ADDR<2>) FDCE symbol `$I2/Q6' (output signal=ADDR<3>) FDCE symbol `$I2/Q7' (output signal=ADDR<4>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q7/$1I35' (output signal=Q<4>) FDCE symbol `$I1/Q0/$1I35' (output signal=$I1/Q<0>) FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>) FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>) FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>) FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>) FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>) FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>) FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q1/$1I35' (output signal=$I1/Q<1>) FDCE symbol `$I1/Q2/$1I35' (output signal=$I1/Q<2>) FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>) FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>) FDCE symbol `$I1/Q5/$1I35' (output signal=Q<2>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:x4kma:191 - The following symbols could not be constrained to a single CLB: FDCE symbol `$I1/Q3/$1I35' (output signal=Q<0>) FDCE symbol `$I1/Q4/$1I35' (output signal=Q<1>) FDCE symbol `$I1/Q6/$1I35' (output signal=Q<3>) T These symbols share the same BLKNM parameter value, which requires them to be mapped to the same CLB. WARNING:baste:164 - Components with same name COUNTER detected...uniquifying. WARNING:baste:164 - Components with same name COUNTER detected...uniquifying. WARNING:baste:164 - Components with same name COUNTER detected...uniquifying. WARNING:baste:164 - Components with same name COUNTER_FD detected...uniquifying. WARNING:baste:164 - Components with same name COUNTER_FD detected...uniquifying. Section: Design Information ---------------------------- Command Line : map -p xc4005xl-1-pc84 -o map.ncd ../xc4000xl.ngd epiclab.pcf Target Device : x4005xl Target Package : pc84 Target Speed : -1 Mapper Version : xc4000xl -- M1.3.7 Mapped Date : Fri Oct 17 08:54:43 1997 Section: Design Attributes --------------------------- Attribute LOC Attribute BLKNM "COUNTER_FD" for signal(s) ADDR<4>, ADDR<3>, ADDR<2>, ADDR<1>, ADDR<0> on symbol "$I2" "WE_FD" for signal(s) WE_REG on symbol "$I23" "COUNTER" for signal(s) Q<4>, Q<3>, Q<2>, Q<1>, Q<0> on symbol "$I1" "D_FD" for signal(s) D_REG on symbol "$I18" "RAM" for signal(s) OUT on symbol "$I3" Attribute OPTIMIZE Attribute OPT_EFFORT Section: Removed Logic ----------------------- Block "$I23/$1I39" (INV) redundant - removed. Block "$I24/$1I46" (INV) redundant - removed. Block "$I24/$1I43" (GND) removed due to optimization. Block "$I24/$1I40" (VCC) removed due to optimization. Block "$I1/$1I16" (VCC) removed due to optimization. The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). The signal "$I2/Q<0>" is loadless and has been removed. Loadless block "$I2/Q0" (FDCE) removed. The signal "$I2/D<0>" is loadless and has been removed. The signal "$I2/CLR" is loadless and has been removed. The signal "$I2/Q<1>" is loadless and has been removed. Loadless block "$I2/Q1" (FDCE) removed. The signal "$I2/D<1>" is loadless and has been removed. The signal "$I2/Q<2>" is loadless and has been removed. Loadless block "$I2/Q2" (FDCE) removed. The signal "$I2/D<2>" is loadless and has been removed. The signal "$I1/CEO" is loadless and has been removed. Loadless block "$I1/$1I31" (AND2) removed. The signal "$I1/TC" is loadless and has been removed. Loadless block "$I1/$1I1/$I1/TC" (X_AND2) removed. The signal "$I1/TC/4.0" is loadless and has been removed. Loadless block "$I1/$1I1/$I1/TC/4.0/$I1/TC/4.0" (X_AND2) removed. The signal "$I1/TC/4.0/2.0" is loadless and has been removed. Loadless block "$I1/$1I1/$I1/TC/4.0/$I1/TC/4.0/2.0" (X_AND2) removed. The signal "$I1/TC/4.0/2.1" is loadless and has been removed. Loadless block "$I1/$1I1/$I1/TC/4.0/$I1/TC/4.0/2.1" (X_AND2) removed. The signal "$I23/CLR" is sourceless and has been removed. The signal "$I1/CLR" is sourceless and has been removed. Merged Signal(s): The signal "$I23/CB" was merged into signal "CLK". The signal "$I24/GB" was merged into signal "CLK". Section: Removed Logic Summary ------------------------------- 8 block(s) clipped 2 block(s) removed 3 block(s) optimized away 14 signal(s) removed 2 signal(s) merged Section: Added Logic --------------------- Section: Expanded Logic ------------------------ "$I1/$1I26" (AND3) expanded into these physical comps: COUNTER.23 (CLB) "$I1/$1I28" (AND4) expanded into these physical comps: COUNTER_FD.5 (CLB) "$I1/$1I11" (AND3) expanded into these physical comps: COUNTER (CLB) "$I1/$1I15" (AND4) expanded into these physical comps: COUNTER_FD.3 (CLB) "$I6" (BUFG) expanded into these physical comps: $I6 (BUFGLS), CLK_IN (CLKIOB) Section: Signal Cross-Reference -------------------------------- Signal "$I1/Q4/TQ" - Driver Comp(s): COUNTER_FD.3 Load Comp(s): COUNTER.23 Signal "$I1/Q<0>" - Driver Comp(s): COUNTER.15 Load Comp(s): COUNTER.15, COUNTER.19, COUNTER.23, COUNTER_FD.3 Signal "$I1/Q<1>" - Driver Comp(s): COUNTER.19 Load Comp(s): COUNTER.19, COUNTER.23, COUNTER_FD.3 Signal "$I1/Q<2>" - Driver Comp(s): COUNTER.19 Load Comp(s): COUNTER.19, COUNTER.23, COUNTER_FD.3 Signal "$I1/T4" - Driver Comp(s): COUNTER_FD.3 Load Comp(s): COUNTER, COUNTER_FD.5 Signal "$I1/T7" - Driver Comp(s): COUNTER_FD.5 Load Comp(s): COUNTER.15 Signal "ADDR<0>" - Driver Comp(s): COUNTER_FD.3 Load Comp(s): RAM Signal "ADDR<1>" - Driver Comp(s): COUNTER_FD.3 Load Comp(s): RAM Signal "ADDR<2>" - Driver Comp(s): COUNTER_FD.5 Load Comp(s): RAM Signal "ADDR<3>" - Driver Comp(s): COUNTER_FD.5 Load Comp(s): RAM Signal "ADDR<4>" - Driver Comp(s): COUNTER_FD Load Comp(s): RAM Signal "CE" - Driver Comp(s): IPAD_CE Load Comp(s): COUNTER, COUNTER.15, COUNTER.19, COUNTER.23, COUNTER_FD, COUNTER_FD.3, COUNTER_FD.5, D_FD, WE_FD Signal "$I24/GB" - Driver Comp(s): $I6 Load Comp(s): COUNTER, COUNTER.15, COUNTER.19, COUNTER.23, COUNTER_FD, COUNTER_FD.3, COUNTER_FD.5, D_FD, RAM, WE_FD Signal "CLK_IN" covered by "CLK_IN" (CLKIOB). Signal "D" - Driver Comp(s): IPAD_D Load Comp(s): D_FD Signal "D_REG" - Driver Comp(s): D_FD Load Comp(s): RAM Signal "IPAD_CE" covered by "IPAD_CE" (IOB). Signal "IPAD_D" covered by "IPAD_D" (IOB). Signal "IPAD_WE" covered by "IPAD_WE" (IOB). Signal "OPAD_OUT_Q" covered by "OPAD_OUT_Q" (IOB). Signal "OUT_Q" - Driver Comp(s): RAM Load Comp(s): OPAD_OUT_Q Signal "Q<0>" - Driver Comp(s): COUNTER.23 Load Comp(s): COUNTER.23, COUNTER_FD.3 Signal "Q<1>" - Driver Comp(s): COUNTER.23 Load Comp(s): COUNTER, COUNTER_FD.3, COUNTER_FD.5 Signal "Q<2>" - Driver Comp(s): COUNTER Load Comp(s): COUNTER, COUNTER_FD.5 Signal "Q<3>" - Driver Comp(s): COUNTER Load Comp(s): COUNTER, COUNTER_FD.5 Signal "Q<4>" - Driver Comp(s): COUNTER.15 Load Comp(s): COUNTER.15, COUNTER_FD Signal "WE" - Driver Comp(s): IPAD_WE Load Comp(s): WE_FD Signal "WE_REG" - Driver Comp(s): WE_FD Load Comp(s): RAM Section: Symbol Cross-reference -------------------------------- "$I1/$1I11" (AND3) mapped to: COUNTER (CLB) "$I1/$1I15" (AND4) mapped to: COUNTER_FD.3 (CLB) "$I1/$1I2" (AND2) mapped to: COUNTER (CLB) "$I1/$1I24" (AND2) mapped to: COUNTER.19 (CLB) "$I1/$1I26" (AND3) mapped to: COUNTER.23 (CLB) "$I1/$1I28" (AND4) mapped to: COUNTER_FD.5 (CLB) "$I1/Q0/$1I32" (XOR2) mapped to: COUNTER.15 (CLB) "$I1/Q0/$1I35" (FDCE) mapped to: COUNTER.15 (CLB) "$I1/Q1/$1I32" (XOR2) mapped to: COUNTER.19 (CLB) "$I1/Q1/$1I35" (FDCE) mapped to: COUNTER.19 (CLB) "$I1/Q2/$1I32" (XOR2) mapped to: COUNTER.19 (CLB) "$I1/Q2/$1I35" (FDCE) mapped to: COUNTER.19 (CLB) "$I1/Q3/$1I32" (XOR2) mapped to: COUNTER.23 (CLB) "$I1/Q3/$1I35" (FDCE) mapped to: COUNTER.23 (CLB) "$I1/Q4/$1I32" (XOR2) mapped to: COUNTER_FD.3 (CLB) "$I1/Q4/$1I35" (FDCE) mapped to: COUNTER.23 (CLB) "$I1/Q5/$1I32" (XOR2) mapped to: COUNTER (CLB) "$I1/Q5/$1I35" (FDCE) mapped to: COUNTER (CLB) "$I1/Q6/$1I32" (XOR2) mapped to: COUNTER (CLB) "$I1/Q6/$1I35" (FDCE) mapped to: COUNTER (CLB) "$I1/Q7/$1I32" (XOR2) mapped to: COUNTER.15 (CLB) "$I1/Q7/$1I35" (FDCE) mapped to: COUNTER.15 (CLB) "$I10" (IBUF) mapped to: IPAD_WE (IOB) "$I11" (IPAD) mapped to: IPAD_WE (IOB) "$I12" (OPAD) mapped to: OPAD_OUT_Q (IOB) "$I18" (FDCE) mapped to: D_FD (CLB) "$I19" (IPAD) mapped to: IPAD_CE (IOB) "$I2/Q3" (FDCE) mapped to: COUNTER_FD.3 (CLB) "$I2/Q4" (FDCE) mapped to: COUNTER_FD.3 (CLB) "$I2/Q5" (FDCE) mapped to: COUNTER_FD.5 (CLB) "$I2/Q6" (FDCE) mapped to: COUNTER_FD.5 (CLB) "$I2/Q7" (FDCE) mapped to: COUNTER_FD (CLB) "$I20" (IBUF) mapped to: IPAD_CE (IOB) "$I23/$1I30" (FDCE) mapped to: WE_FD (CLB) "$I24/$1I37" (LDCE_1) mapped to: RAM (CLB) "$I3" (RAM32X1S) mapped to: RAM (CLB) "$I4" (IPAD) mapped to: IPAD_D (IOB) "$I5" (IBUF) mapped to: IPAD_D (IOB) "$I6" (BUFG) mapped to: $I6 (BUFGLS), CLK_IN (CLKIOB) "$I7" (OBUF) mapped to: OPAD_OUT_Q (IOB) "$I9" (IPAD) mapped to: CLK_IN (CLKIOB) Section: Physical Design Log ----------------------------- Section: Physical Design Errors and Warnings --------------------------------------------- Section: IOB Properties ------------------------ "OPAD_OUT_Q" (IOB) : SLEW=SLOW Section: RPMs -------------- Section: Guide Report ---------------------- Guide not run on this design. Section: Design Summary ------------------------ Number of warnings: 32 Number of errors: 0 Number of CLBs: 10 out of 196 Flops/latches: 16 4 input LUTs: 12 3 input LUTs: 7 Number of bonded IOBs: 5 out of 63 Number of clock IOBs: 1 out of 12 Number of BUFGLSs: 1 out of 8