Xilinx Mapping Report File for Design "ROOT" Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design Information ------------------ Command Line : map -fp calc_r.mfp -p 4003e-pc84-1 calc Target Device : x4003e Target Package : pc84 Target Speed : -1 Mapper Version : xc4000e -- M1.5.19 Mapped Date : Thu Sep 03 15:32:24 1998 Design Summary -------------- Number of errors: 0 Number of warnings: 29 Number of CLBs: 33 out of 100 33% CLB Flip Flops: 11 4 input LUTs: 50 (2 used as route-throughs) 3 input LUTs: 14 16X1 RAMs: 4 Number of bonded IOBs: 25 out of 61 40% IOB Flops: 8 IOB Latches: 0 Number of secondary CLKs: 1 out of 4 25% Number of oscillators: 1 Number of STARTUPs: 1 Total equivalent gate count for design: 742 Additional JTAG gate count for IOBs: 1200 Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Design Attributes Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - Added Logic Section 7 - Expanded Logic Section 8 - Signal Cross-Reference Section 9 - Symbol Cross-Reference Section 10 - IOB Properties Section 11 - RPMs Section 12 - Guide Report Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:basnu:113 - logical net "LIFO/$1I173/CEO" has no load WARNING:x4kma:390 - Deleting LOC and RLOC_ORIGIN constraints on all comps except edge decoders. WARNING:x4kma:391 - Deleting LOC P49 on comp A. WARNING:x4kma:391 - Deleting LOC P48 on comp B. WARNING:x4kma:391 - Deleting LOC P47 on comp C. WARNING:x4kma:391 - Deleting LOC P46 on comp D. WARNING:x4kma:391 - Deleting LOC P45 on comp E. WARNING:x4kma:391 - Deleting LOC P50 on comp F. WARNING:x4kma:391 - Deleting LOC P51 on comp G. WARNING:x4kma:391 - Deleting LOC P66 on comp GAUGE0. WARNING:x4kma:391 - Deleting LOC P65 on comp GAUGE1. WARNING:x4kma:391 - Deleting LOC P62 on comp GAUGE2. WARNING:x4kma:391 - Deleting LOC P61 on comp GAUGE3. WARNING:x4kma:391 - Deleting LOC P56 on comp NOTGBLRESET. WARNING:x4kma:391 - Deleting LOC P41 on comp OFL. WARNING:x4kma:391 - Deleting LOC P60 on comp STACKLED0. WARNING:x4kma:391 - Deleting LOC P59 on comp STACKLED1. WARNING:x4kma:391 - Deleting LOC P58 on comp STACKLED2. WARNING:x4kma:391 - Deleting LOC P57 on comp STACKLED3. WARNING:x4kma:391 - Deleting LOC P28 on comp SWITCH0. WARNING:x4kma:391 - Deleting LOC P27 on comp SWITCH1. WARNING:x4kma:391 - Deleting LOC P26 on comp SWITCH2. WARNING:x4kma:391 - Deleting LOC P25 on comp SWITCH3. WARNING:x4kma:391 - Deleting LOC P24 on comp SWITCH4. WARNING:x4kma:391 - Deleting LOC P23 on comp SWITCH5. WARNING:x4kma:391 - Deleting LOC P20 on comp SWITCH6. WARNING:x4kma:391 - Deleting LOC P19 on comp SWITCH7. WARNING:baste - Only 104 out of 106 floorplan bel constraints were matched to the logical design (NGD). Non-matches are often caused by using an MFP file that was created from an earlier version of the design source files. Having some, but not all constraints from the MFP file match with objects in the source file can cause inefficient implementations, and possibly CLB packing errors. When changes are made to source files (i.e. a new Version is created) it is recommended that MAP be run initially without the floorplan constraints (-fp) option. Then a new MFP file can be generated in the Floorplanner after reading in the mapped NCD file and correlating the constraints generated in the previous version of the Floorplanner netist file (FNF). WARNING:x4kma:111 - All the logic for FMAP symbol "ARITH/ADDSUB/$1I293" (output signal=ARITH/ADDSUB/OFL) has been removed! This may be caused by key logic being trimmed. Please consult the Removed Logic section of this report to see if this is the case. Section 3 - Design Attributes ----------------------------- Attribute LOC "P24" on symbol "$1I572/$1I30" "P23" on symbol "$1I572/$1I31" "P20" on symbol "$1I572/$1I32" "P19" on symbol "$1I572/$1I33" "P25" on symbol "$1I572/$1I34" "P26" on symbol "$1I572/$1I35" "P27" on symbol "$1I572/$1I36" "P28" on symbol "$1I572/$1I37" "P56" on symbol "$1I492" "P66" for signal(s) GAUGE0 on symbol "$1I597" "P41" for signal(s) OFL on symbol "$1I516" "P49" for signal(s) A on symbol "$1I530" "P48" for signal(s) B on symbol "$1I533" "P47" for signal(s) C on symbol "$1I535" "P46" for signal(s) D on symbol "$1I537" "P45" for signal(s) E on symbol "$1I539" "P50" for signal(s) F on symbol "$1I541" "P51" for signal(s) G on symbol "$1I543" "P57" for signal(s) STACKLED3 on symbol "$1I549" "P58" for signal(s) STACKLED2 on symbol "$1I557" "P59" for signal(s) STACKLED1 on symbol "$1I563" "P60" for signal(s) STACKLED0 on symbol "$1I569" "P61" for signal(s) GAUGE3 on symbol "$1I588" "P62" for signal(s) GAUGE2 on symbol "$1I591" "P65" for signal(s) GAUGE1 on symbol "$1I594" Section 4 - Removed Logic Summary --------------------------------- 37 block(s) removed 23 block(s) optimized away 37 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). The signal "LIFO/$1I173/CEO" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I50" (AND2) removed. The signal "LIFO/$1I173/TC" is loadless and has been removed. Loadless block "LIFO/$1I173/TC/$1I8" (OR2) removed. The signal "LIFO/$1I173/TC/M1" is loadless and has been removed. Loadless block "LIFO/$1I173/TC/$1I9" (AND2) removed. The signal "LIFO/$1I173/TC_UP" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I10/LIFO/$1I173/TC_UP" (X_AND2) removed. The signal "LIFO/$1I173/TC_UP/2.0" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I10/LIFO/$1I173/TC_UP/2.0" (X_AND2) removed. The signal "LIFO/$1I173/TC_UP/2.1" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I10/LIFO/$1I173/TC_UP/2.1" (X_AND2) removed. The signal "LIFO/$1I173/Q3" is loadless and has been removed. Loadless block "LIFO/$1I173/Q3/$1I35" (FDCE) removed. The signal "LIFO/$1I173/Q3/MD" is loadless and has been removed. Loadless block "LIFO/$1I173/Q3/$1I30/$1I8" (OR2) removed. The signal "LIFO/$1I173/Q3/$1I30/M1" is loadless and has been removed. Loadless block "LIFO/$1I173/Q3/$1I30/$1I9" (AND2) removed. The signal "LIFO/$1I173/Q3/$1I30/M0" is loadless and has been removed. Loadless block "LIFO/$1I173/Q3/$1I30/$1I7" (AND2B1) removed. The signal "LIFO/$1I173/Q3/TQ" is loadless and has been removed. Loadless block "LIFO/$1I173/Q3/$1I32" (XOR2) removed. The signal "LIFO/$1I173/T3" is loadless and has been removed. Loadless block "LIFO/$1I173/T3/$1I8" (OR2) removed. The signal "LIFO/$1I173/T3/M1" is loadless and has been removed. Loadless block "LIFO/$1I173/T3/$1I9" (AND2) removed. The signal "LIFO/$1I173/T3_UP" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I15/LIFO/$1I173/T3_UP" (X_AND2) removed. The signal "LIFO/$1I173/T3_UP/2.0" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I15/LIFO/$1I173/T3_UP/2.0" (X_AND2) removed. The signal "LIFO/$1I173/T3/M0" is loadless and has been removed. Loadless block "LIFO/$1I173/T3/$1I7" (AND2B1) removed. The signal "LIFO/$1I173/T3_DN" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I16/LIFO/$1I173/T3_DN" (X_AND2) removed. The signal "LIFO/$1I173/T3_DN/2.0" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I16/LIFO/$1I173/T3_DN/2.0" (X_AND2) removed. The signal "LIFO/$1I173/TC/M0" is loadless and has been removed. Loadless block "LIFO/$1I173/TC/$1I7" (AND2B1) removed. The signal "LIFO/$1I173/TC_DN" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I11/LIFO/$1I173/TC_DN" (X_AND2) removed. The signal "LIFO/$1I173/TC_DN/2.0" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I11/LIFO/$1I173/TC_DN/2.0" (X_AND2) removed. The signal "LIFO/$1I173/TC_DN/2.1" is loadless and has been removed. Loadless block "LIFO/$1I173/$1I11/LIFO/$1I173/TC_DN/2.1" (X_AND2) removed. The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic The signal "ARITH/ADDSUB/$1N259" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I260/ARITH/ADDSUB/$1N259" (X_OR2) removed. The signal "ARITH/ADDSUB/$1N259/2.0" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I260/ARITH/ADDSUB/$1N259/2.0" (X_OR2) removed. The signal "ARITH/ADDSUB/OOR1" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I266" (AND2) removed. The signal "ARITH/ADDSUB/B3_M1" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I271" (XNOR2) removed. The signal "ARITH/ADDSUB/OOR2" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I270" (AND2) removed. The signal "ARITH/ADDSUB/OOR3" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I264" (AND2) removed. The signal "ARITH/ADDSUB/OFL" is unused and has been removed. Unused block "ARITH/ADDSUB/$1I305" (XOR2) removed. The signal "$1I505/$1I1/$1N41" is unused and has been removed. Unused block "$1I505/$1I1/$1I40" (VCC) removed. The signal "$1I502/$1I2/$1N41" is unused and has been removed. Unused block "$1I502/$1I2/$1I40" (VCC) removed. The signal "$1I502/$1I3/$1N41" is unused and has been removed. Unused block "$1I502/$1I3/$1I40" (VCC) removed. The signal "$1I502/$1I4/$1N41" is unused and has been removed. Unused block "$1I502/$1I4/$1I40" (VCC) removed. The signal "$1I502/$1I5/$1N41" is unused and has been removed. Unused block "$1I502/$1I5/$1I40" (VCC) removed. The signal "$1I502/$1I6/$1N41" is unused and has been removed. Unused block "$1I502/$1I6/$1I40" (VCC) removed. The signal "$1I502/$1I7/$1N41" is unused and has been removed. Unused block "$1I502/$1I7/$1I40" (VCC) removed. The signal "$1I502/$1I8/$1N41" is unused and has been removed. Unused block "$1I502/$1I8/$1I40" (VCC) removed. Optimized Block(s): TYPE BLOCK VCC $1I505/$1I2/$1I40 GND $1I505/$1I2/$1I43 VCC $1I505/$1I4/$1I40 GND $1I505/$1I4/$1I43 VCC ARITH/ALUVAL/Q0/$1I42/$1I40 GND ARITH/ALUVAL/Q0/$1I42/$1I43 VCC ARITH/ALUVAL/Q1/$1I42/$1I40 GND ARITH/ALUVAL/Q1/$1I42/$1I43 VCC ARITH/ALUVAL/Q2/$1I42/$1I40 GND ARITH/ALUVAL/Q2/$1I42/$1I43 VCC ARITH/ALUVAL/Q3/$1I42/$1I40 GND ARITH/ALUVAL/Q3/$1I42/$1I43 VCC ARITH/MUXBLK5/$1I89 VCC ARITH/OVERFLOW/$1I42/$1I40 GND ARITH/OVERFLOW/$1I42/$1I43 VCC LIFO/$1I172/$1I573/$1I40 GND LIFO/$1I172/$1I573/$1I43 VCC LIFO/$1I173/$1I1 GND LIFO/$1I183 AND2 LIFO/$1I173/Q0/$1I30/$1I9 AND2 LIFO/$1I173/Q1/$1I30/$1I9 AND2 LIFO/$1I173/Q2/$1I30/$1I9 GND LIFO/$1I180 To enable printing of redundant blocks removed and signals merged, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map. Section 6 - Added Logic ----------------------- Section 7 - Expanded Logic -------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 8 - Signal Cross-Reference ---------------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 9 - Symbol Cross-Reference ---------------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 10 - IOB Properties --------------------------- A (IOB) : SLEW=SLOW B (IOB) : SLEW=SLOW C (IOB) : SLEW=SLOW D (IOB) : SLEW=SLOW E (IOB) : SLEW=SLOW F (IOB) : SLEW=SLOW G (IOB) : SLEW=SLOW GAUGE0 (IOB) : SLEW=SLOW GAUGE1 (IOB) : SLEW=SLOW GAUGE2 (IOB) : SLEW=SLOW GAUGE3 (IOB) : SLEW=SLOW OFL (IOB) : SLEW=SLOW STACKLED0 (IOB) : SLEW=FAST STACKLED1 (IOB) : SLEW=FAST STACKLED2 (IOB) : SLEW=FAST STACKLED3 (IOB) : SLEW=FAST SWITCH0 (IOB) : INFF SWITCH1 (IOB) : INFF SWITCH2 (IOB) : INFF SWITCH3 (IOB) : INFF SWITCH4 (IOB) : INFF SWITCH5 (IOB) : INFF SWITCH6 (IOB) : INFF SWITCH7 (IOB) : INFF Section 11 - RPMs ----------------- Section 12 - Guide Report ------------------------- Guide not run on this design.