PAR: Xilinx Place And Route M1.5.19. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Mon Jul 06 14:37:32 1998 par -c 0 calc calc_r Constraints file: calc.pcf Loading device database for application par from file "calc.ncd". "ROOT" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application par from file '4003e.nph' in environment g:/rtf/x1_5.19. Device speed data version: x1_0.95 PRELIMINARY. Resolved that IOB must be placed at site P49. Place IOB A in site P49. Resolved that IOB must be placed at site P48. Place IOB B in site P48. Resolved that IOB must be placed at site P47. Place IOB C in site P47. Resolved that IOB must be placed at site P46. Place IOB D in site P46. Resolved that IOB must be placed at site P45. Place IOB E in site P45. Resolved that IOB must be placed at site P50. Place IOB F in site P50. Resolved that IOB must be placed at site P51. Place IOB G in site P51. Resolved that IOB must be placed at site P66. Place IOB GAUGE0 in site P66. Resolved that IOB must be placed at site P65. Place IOB GAUGE1 in site P65. Resolved that IOB must be placed at site P62. Place IOB GAUGE2 in site P62. Resolved that IOB must be placed at site P61. Place IOB GAUGE3 in site P61. Resolved that IOB must be placed at site P56. Place IOB NOTGBLRESET in site P56. Resolved that IOB must be placed at site P41. Place IOB OFL in site P41. Resolved that IOB must be placed at site P60. Place IOB STACKLED0 in site P60. Resolved that IOB must be placed at site P59. Place IOB STACKLED1 in site P59. Resolved that IOB must be placed at site P58. Place IOB STACKLED2 in site P58. Resolved that IOB must be placed at site P57. Place IOB STACKLED3 in site P57. Resolved that IOB must be placed at site P28. Place IOB SWITCH0 in site P28. Resolved that IOB must be placed at site P27. Place IOB SWITCH1 in site P27. Resolved that IOB must be placed at site P26. Place IOB SWITCH2 in site P26. Resolved that IOB must be placed at site P25. Place IOB SWITCH3 in site P25. Resolved that IOB must be placed at site P24. Place IOB SWITCH4 in site P24. Resolved that IOB must be placed at site P23. Place IOB SWITCH5 in site P23. Resolved that IOB must be placed at site P20. Place IOB SWITCH6 in site P20. Resolved that IOB must be placed at site P19. Place IOB SWITCH7 in site P19. Device utilization summary: Number of External IOBs 25 out of 61 40% Flops: 8 Latches: 0 Number of CLBs 32 out of 100 32% Total CLB Flops: 11 out of 200 5% 4 input LUTs: 54 out of 200 27% 3 input LUTs: 14 out of 100 14% Number of OSCILLATORs 1 out of 1 100% Number of SEC-CLKs 1 out of 4 25% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): 2 (default) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 11 secs Starting Constructive Placer. REAL time: 11 secs Placer score = 34320 Placer score = 30420 Placer score = 26280 Placer score = 23340 Placer score = 21840 Finished Constructive Placer. REAL time: 12 secs Writing design to file "calc_r.ncd". Starting Optimizing Placer. REAL time: 12 secs Optimizing Swapped 27 comps. Xilinx Placer [1] 19500 REAL time: 12 secs Finished Optimizing Placer. REAL time: 12 secs Writing design to file "calc_r.ncd". Total REAL time to Placer completion: 12 secs Total CPU time to Placer completion: 4 secs DEBUG - Building X4K_RT_ASTAR DEBUG - X4K_RT_ASTAR::delay_hstar_scale = 4.960082e-315 0 connection(s) routed; 248 unrouted active, 4 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 12 secs Starting iterative routing. Routing active signals. End of iteration 1 248 successful; 0 unrouted active, 4 unrouted PWR/GND; (0) REAL time: 13 secs End of iteration 2 248 successful; 0 unrouted active, 4 unrouted PWR/GND; (0) REAL time: 13 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Total REAL time: 13 secs Total CPU time: 5 secs End of route. 252 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 14 secs Total CPU time to Router completion: 5 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 322 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 2.225 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.078 ns The Maximum Pin Delay is: 6.252 ns The Average Connection Delay on the 10 Worst Nets is: 4.998 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 252 0 0 0 0 0 Writing design to file "calc_r.ncd". All signals are completely routed. Total REAL time to PAR completion: 15 secs Total CPU time to PAR completion: 6 secs PAR done.