ngdbuild -p xc4003e-1-pc84 -dd .. C:\davin\fplanlabs_d\calc_fp\calc.xnf calc.ngd ngdbuild: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4003e-1-pc84 -dd .. C:\davin\fplanlabs_d\calc_fp\calc.xnf calc.ngd Launcher: Executing xnf2ngd -p xc4000e -u "C:\davin\fplanlabs_d\calc_fp\calc.xnf" "C:\davin\fplanlabs_d\calc_fp\xproj\ver1\calc.ngo" xnf2ngd: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. using XNF gate model reading XNF file "C:/davin/fplanlabs_d/calc_fp/calc.xnf" ... WARNING:basxn:6 - Signal "COUT$c8" has only one connection. Writing NGO file "C:/davin/fplanlabs_d/calc_fp/xproj/ver1/calc.ngo" ... Reading NGO file "C:/davin/fplanlabs_d/calc_fp/xproj/ver1/calc.ngo" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... WARNING:basnu:113 - logical net "COUT$c8" has no load NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 1 Writing NGD file "calc.ngd" ... Writing NGDBUILD log file "calc.bld"... NGDBUILD done. ================================================== map -p xc4003e-1-pc84 -o map.ncd calc.ngd calc.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "calc.ngd"... Using target part "4003epc84-1". MAP xc4000e directives: Partname = "xc4003e-1-pc84". Covermode = "area". Pack CLBs to 97%. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 2 Number of CLBs: 4 out of 100 4% CLB Flip Flops: 8 4 input LUTs: 8 3 input LUTs: 0 Number of bonded IOBs: 11 out of 61 18% IOB Flops: 8 IOB Latches: 0 Number of clock IOB pads: 1 out of 8 12% Number of primary CLKs: 1 out of 4 25% Number of STARTUPs: 1 Total equivalent gate count for design: 193 Additional JTAG gate count for IOBs: 528 Writing design file "map.ncd"... Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd calc.ncd calc.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: calc.pcf Loading device database for application par from file "map.ncd". "calc" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application par from file '4003e.nph' in environment C:/fndtn. ABORTING ================================================== par -w -ol 2 -d 0 map.ncd calc.ncd calc.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: calc.pcf Loading device database for application par from file "map.ncd". "calc" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application par from file '4003e.nph' in environment C:/fndtn. Device speed data version: x1_0.95 PRELIMINARY. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 10 out of 61 16% Flops: 8 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 4 out of 100 4% Total CLB Flops: 8 out of 200 4% 4 input LUTs: 8 out of 200 4% 3 input LUTs: 0 out of 100 1% Number of PRI-CLKs 1 out of 4 25% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Starting initial Placement phase. REAL time: 4 secs Finished initial Placement phase. REAL time: 4 secs Starting Constructive Placer. REAL time: 4 secs Placer score = 5640 Finished Constructive Placer. REAL time: 5 secs Writing design to file "calc.ncd". Starting Optimizing Placer. REAL time: 5 secs Optimizing Swapped 39 comps. Xilinx Placer [1] 2040 REAL time: 5 secs Finished Optimizing Placer. REAL time: 5 secs Writing design to file "calc.ncd". Total REAL time to Placer completion: 5 secs Total CPU time to Placer completion: 3 secs 0 connection(s) routed; 45 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 5 secs Starting iterative routing. Routing active signals. End of iteration 1 45 successful; 0 unrouted; (0) REAL time: 5 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "calc.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 45 successful; 0 unrouted; (0) REAL time: 5 secs Writing design to file "calc.ncd". Total REAL time: 5 secs Total CPU time: 3 secs End of route. 45 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 5 secs Total CPU time to Router completion: 4 secs Generating PAR statistics. Writing design to file "calc.ncd". All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 4 secs PAR done. ================================================== map -p xc4003e-1-pc84 -o map.ncd calc.ngd calc.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "calc.ngd"... Using target part "4003epc84-1". MAP xc4000e directives: Partname = "xc4003e-1-pc84". Covermode = "area". Pack CLBs to 97%. Processing logical timing constraints... Running general design DRC... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 2 Number of CLBs: 32 out of 100 32% CLB Flip Flops: 11 4 input LUTs: 50 (2 used as route-throughs) 3 input LUTs: 14 16X1 RAMs: 4 Number of bonded IOBs: 25 out of 61 40% IOB Flops: 8 IOB Latches: 0 Number of secondary CLKs: 1 out of 4 25% Number of RPM macros: 1 Number of oscillators: 1 Number of STARTUPs: 1 Total equivalent gate count for design: 742 Additional JTAG gate count for IOBs: 1200 ** Writing MDF file map.mdf for NCD output file map.ncd. ** Always use the MDF file with the guide NCD file for best results. Writing design file "map.ncd"... Removed Logic Summary: 37 block(s) removed 23 block(s) optimized away 37 signal(s) removed Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd calc.ncd calc.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: calc.pcf Loading device database for application par from file "map.ncd". "ROOT" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application par from file '4003e.nph' in environment C:/fndtn. Device speed data version: x1_0.95 PRELIMINARY. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 25 out of 61 40% Flops: 8 Latches: 0 Number of CLBs 32 out of 100 32% Total CLB Flops: 11 out of 200 5% 4 input LUTs: 54 out of 200 27% 3 input LUTs: 14 out of 100 14% Number of OSCILLATORs 1 out of 1 100% Number of SEC-CLKs 1 out of 4 25% Number of STARTUPs 1 out of 1 100% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Starting initial Placement phase. REAL time: 4 secs Finished initial Placement phase. REAL time: 4 secs Starting Constructive Placer. REAL time: 4 secs Placer score = 34320 Placer score = 30420 Placer score = 26280 Placer score = 23340 Placer score = 21840 Finished Constructive Placer. REAL time: 4 secs Writing design to file "calc.ncd". Starting Optimizing Placer. REAL time: 4 secs Optimizing Swapped 27 comps. Xilinx Placer [1] 19500 REAL time: 5 secs Finished Optimizing Placer. REAL time: 5 secs Writing design to file "calc.ncd". Total REAL time to Placer completion: 5 secs Total CPU time to Placer completion: 4 secs 0 connection(s) routed; 248 unrouted active, 4 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 5 secs Starting iterative routing. Routing active signals. End of iteration 1 248 successful; 0 unrouted active, 4 unrouted PWR/GND; (0) REAL time: 5 secs End of iteration 2 248 successful; 0 unrouted active, 4 unrouted PWR/GND; (0) REAL time: 6 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "calc.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 252 successful; 0 unrouted; (0) REAL time: 9 secs Writing design to file "calc.ncd". Total REAL time: 9 secs Total CPU time: 8 secs End of route. 252 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 9 secs Total CPU time to Router completion: 8 secs Generating PAR statistics. Writing design to file "calc.ncd". All signals are completely routed. Total REAL time to PAR completion: 10 secs Total CPU time to PAR completion: 9 secs PAR done. ================================================== trce calc.ncd calc.pcf -e 3 -o calc.twr Loading device database for application trce from file "calc.ncd". "ROOT" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application trce from file '4003e.nph' in environment C:/fndtn. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.21 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: calc.ncd Physical constraint file: calc.pcf Device,speed: xc4003e,-1 (x1_0.95 PRELIMINARY) Report level: error report, limited to 3 items per constraint -------------------------------------------------------------------------------- WARNING:bastw:170 - No timing constraints found, doing default enumeration. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 963 paths, 81 nets, and 248 connections (100.0% coverage) Design statistics: Minimum period: 26.481ns (Maximum frequency: 37.763MHz) Maximum net delay: 6.252ns WARNING:bastw:544 - Clock nets using non-dedicated resources were found in this design. Clock skew on these resources will not be automatically addressed during path analysis. To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option. Analysis completed Tue Oct 13 09:04:56 1998 -------------------------------------------------------------------------------- Total time: 5 secs ================================================== bitgen calc.ncd -l -w -f bitgen.ut Loading device database for application Bitgen from file "calc.ncd". "ROOT" is an NCD, version 2.27, device xc4003e, package pc84, speed -1 Loading device for application Bitgen from file '4003e.nph' in environment C:/fndtn. ABORTING