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Xilinx TRACE, Version M1.5.21
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Design file:              calc.ncd
Physical constraint file: calc.pcf
Device,speed:             xc4003e,-1 (x1_0.95  PRELIMINARY)
Report level:             error report, limited to 3 items per constraint
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WARNING:bastw:170 - No timing constraints found, doing default enumeration.

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Timing constraint: Default period analysis
 963 items analyzed, 0 timing errors detected.
 Minimum period is  26.481ns.
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================================================================================
Timing constraint: Default net enumeration
 81 items analyzed, 0 timing errors detected.
 Maximum net delay is   6.252ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 963 paths, 81 nets, and 248 connections (100.0% coverage)

Design statistics:
   Minimum period:  26.481ns (Maximum frequency:  37.763MHz)
   Maximum net delay:   6.252ns

WARNING:bastw:544 - Clock nets using non-dedicated resources were found in this
   design. Clock skew on these resources will not be automatically addressed
   during path analysis. To create a timing report that analyzes clock skew for
   these paths, run trce with the '-skew' option.

Analysis completed Tue Oct 13 09:04:56 1998
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