PAR: Xilinx Place And Route M1.5.19.
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Tue Jun 30 15:16:22 1998

par -l 4 -d 1 pci_top pci_top_fpr -w


Constraints file: pci_top.pcf

Loading device database for application par from file "pci_top.ncd".
   "pci_top" is an NCD, version 2.27, device xcs40, package pq240, speed -4
Loading device for application par from file '4020e.nph' in environment
/build/xfndry/rtf/x1_5.19.
Device speed data version:  x1_0.14 1.6 PRELIMINARY.


Resolved that IOB <AD<0>> must be placed at site P78.
   Place IOB AD<0> in site P78.
Resolved that IOB <AD<10>> must be placed at site P52.
   Place IOB AD<10> in site P52.
Resolved that IOB <AD<11>> must be placed at site P51.
   Place IOB AD<11> in site P51.
Resolved that IOB <AD<12>> must be placed at site P50.
   Place IOB AD<12> in site P50.
Resolved that IOB <AD<13>> must be placed at site P49.
   Place IOB AD<13> in site P49.
Resolved that IOB <AD<14>> must be placed at site P48.
   Place IOB AD<14> in site P48.
Resolved that IOB <AD<15>> must be placed at site P44.
   Place IOB AD<15> in site P44.
Resolved that IOB <AD<16>> must be placed at site P20.
   Place IOB AD<16> in site P20.
Resolved that IOB <AD<17>> must be placed at site P15.
   Place IOB AD<17> in site P15.
Resolved that IOB <AD<18>> must be placed at site P11.
   Place IOB AD<18> in site P11.
Resolved that IOB <AD<19>> must be placed at site P10.
   Place IOB AD<19> in site P10.
Resolved that IOB <AD<1>> must be placed at site P76.
   Place IOB AD<1> in site P76.
Resolved that IOB <AD<20>> must be placed at site P9.
   Place IOB AD<20> in site P9.
Resolved that IOB <AD<21>> must be placed at site P8.
   Place IOB AD<21> in site P8.
Resolved that IOB <AD<22>> must be placed at site P5.
   Place IOB AD<22> in site P5.
Resolved that IOB <AD<23>> must be placed at site P3.
   Place IOB AD<23> in site P3.
Resolved that IOB <AD<24>> must be placed at site P233.
   Place IOB AD<24> in site P233.
Resolved that IOB <AD<25>> must be placed at site P232.
   Place IOB AD<25> in site P232.
Resolved that IOB <AD<26>> must be placed at site P231.
   Place IOB AD<26> in site P231.
Resolved that IOB <AD<27>> must be placed at site P230.
   Place IOB AD<27> in site P230.
Resolved that IOB <AD<28>> must be placed at site P229.
   Place IOB AD<28> in site P229.
Resolved that IOB <AD<29>> must be placed at site P228.
   Place IOB AD<29> in site P228.
Resolved that IOB <AD<2>> must be placed at site P72.
   Place IOB AD<2> in site P72.
Resolved that IOB <AD<30>> must be placed at site P226.
   Place IOB AD<30> in site P226.
Resolved that IOB <AD<31>> must be placed at site P224.
   Place IOB AD<31> in site P224.
Resolved that IOB <AD<3>> must be placed at site P71.
   Place IOB AD<3> in site P71.
Resolved that IOB <AD<4>> must be placed at site P70.
   Place IOB AD<4> in site P70.
Resolved that IOB <AD<5>> must be placed at site P69.
   Place IOB AD<5> in site P69.
Resolved that IOB <AD<6>> must be placed at site P67.
   Place IOB AD<6> in site P67.
Resolved that IOB <AD<7>> must be placed at site P66.
   Place IOB AD<7> in site P66.
Resolved that IOB <AD<8>> must be placed at site P54.
   Place IOB AD<8> in site P54.
Resolved that IOB <AD<9>> must be placed at site P53.
   Place IOB AD<9> in site P53.
Resolved that IOB <CBE<0>> must be placed at site P65.
   Place IOB CBE<0> in site P65.
Resolved that IOB <CBE<1>> must be placed at site P43.
   Place IOB CBE<1> in site P43.
Resolved that IOB <CBE<2>> must be placed at site P21.
   Place IOB CBE<2> in site P21.
Resolved that IOB <CBE<3>> must be placed at site P236.
   Place IOB CBE<3> in site P236.
Resolved that IOB <DEVSEL_N> must be placed at site P27.
   Place IOB DEVSEL_N in site P27.
Resolved that IOB <FRAME_N> must be placed at site P24.
   Place IOB FRAME_N in site P24.
Resolved that IOB <GNT_N> must be placed at site P23.
   Place IOB GNT_N in site P23.
Resolved that IOB <IDSEL> must be placed at site P237.
   Place IOB IDSEL in site P237.
Resolved that IOB <IF_ADDR<10>> must be placed at site P146.
   Place IOB IF_ADDR<10> in site P146.
Resolved that IOB <IF_ADDR<11>> must be placed at site P147.
   Place IOB IF_ADDR<11> in site P147.
Resolved that IOB <IF_ADDR<12>> must be placed at site P148.
   Place IOB IF_ADDR<12> in site P148.
Resolved that IOB <IF_ADDR<13>> must be placed at site P149.
   Place IOB IF_ADDR<13> in site P149.
Resolved that IOB <IF_ADDR<14>> must be placed at site P152.
   Place IOB IF_ADDR<14> in site P152.
Resolved that IOB <IF_ADDR<15>> must be placed at site P153.
   Place IOB IF_ADDR<15> in site P153.
Resolved that IOB <IF_ADDR<2>> must be placed at site P136.
   Place IOB IF_ADDR<2> in site P136.
Resolved that IOB <IF_ADDR<3>> must be placed at site P137.
   Place IOB IF_ADDR<3> in site P137.
Resolved that IOB <IF_ADDR<4>> must be placed at site P138.
   Place IOB IF_ADDR<4> in site P138.
Resolved that IOB <IF_ADDR<5>> must be placed at site P139.
   Place IOB IF_ADDR<5> in site P139.
Resolved that IOB <IF_ADDR<6>> must be placed at site P141.
   Place IOB IF_ADDR<6> in site P141.
Resolved that IOB <IF_ADDR<7>> must be placed at site P142.
   Place IOB IF_ADDR<7> in site P142.
Resolved that IOB <IF_ADDR<8>> must be placed at site P144.
   Place IOB IF_ADDR<8> in site P144.
Resolved that IOB <IF_ADDR<9>> must be placed at site P145.
   Place IOB IF_ADDR<9> in site P145.
Resolved that IOB <IRDY_N> must be placed at site P25.
   Place IOB IRDY_N in site P25.
Resolved that IOB <IRF_AE> must be placed at site P155.
   Place IOB IRF_AE in site P155.
Resolved that IOB <IRF_DOUT<0>> must be placed at site P114.
   Place IOB IRF_DOUT<0> in site P114.
Resolved that IOB <IRF_DOUT<10>> must be placed at site P129.
   Place IOB IRF_DOUT<10> in site P129.
Resolved that IOB <IRF_DOUT<11>> must be placed at site P130.
   Place IOB IRF_DOUT<11> in site P130.
Resolved that IOB <IRF_DOUT<12>> must be placed at site P131.
   Place IOB IRF_DOUT<12> in site P131.
Resolved that IOB <IRF_DOUT<13>> must be placed at site P132.
   Place IOB IRF_DOUT<13> in site P132.
Resolved that IOB <IRF_DOUT<14>> must be placed at site P133.
   Place IOB IRF_DOUT<14> in site P133.
Resolved that IOB <IRF_DOUT<15>> must be placed at site P134.
   Place IOB IRF_DOUT<15> in site P134.
Resolved that IOB <IRF_DOUT<16>> must be placed at site P162.
   Place IOB IRF_DOUT<16> in site P162.
Resolved that IOB <IRF_DOUT<17>> must be placed at site P163.
   Place IOB IRF_DOUT<17> in site P163.
Resolved that IOB <IRF_DOUT<18>> must be placed at site P164.
   Place IOB IRF_DOUT<18> in site P164.
Resolved that IOB <IRF_DOUT<19>> must be placed at site P165.
   Place IOB IRF_DOUT<19> in site P165.
Resolved that IOB <IRF_DOUT<1>> must be placed at site P115.
   Place IOB IRF_DOUT<1> in site P115.
Resolved that IOB <IRF_DOUT<20>> must be placed at site P167.
   Place IOB IRF_DOUT<20> in site P167.
Resolved that IOB <IRF_DOUT<21>> must be placed at site P168.
   Place IOB IRF_DOUT<21> in site P168.
Resolved that IOB <IRF_DOUT<22>> must be placed at site P169.
   Place IOB IRF_DOUT<22> in site P169.
Resolved that IOB <IRF_DOUT<23>> must be placed at site P170.
   Place IOB IRF_DOUT<23> in site P170.
Resolved that IOB <IRF_DOUT<24>> must be placed at site P171.
   Place IOB IRF_DOUT<24> in site P171.
Resolved that IOB <IRF_DOUT<25>> must be placed at site P172.
   Place IOB IRF_DOUT<25> in site P172.
Resolved that IOB <IRF_DOUT<26>> must be placed at site P173.
   Place IOB IRF_DOUT<26> in site P173.
Resolved that IOB <IRF_DOUT<27>> must be placed at site P174.
   Place IOB IRF_DOUT<27> in site P174.
Resolved that IOB <IRF_DOUT<28>> must be placed at site P175.
   Place IOB IRF_DOUT<28> in site P175.
Resolved that IOB <IRF_DOUT<29>> must be placed at site P176.
   Place IOB IRF_DOUT<29> in site P176.
Resolved that IOB <IRF_DOUT<2>> must be placed at site P116.
   Place IOB IRF_DOUT<2> in site P116.
Resolved that IOB <IRF_DOUT<30>> must be placed at site P183.
   Place IOB IRF_DOUT<30> in site P183.
Resolved that IOB <IRF_DOUT<31>> must be placed at site P184.
   Place IOB IRF_DOUT<31> in site P184.
Resolved that IOB <IRF_DOUT<32>> must be placed at site P185.
   Place IOB IRF_DOUT<32> in site P185.
Resolved that IOB <IRF_DOUT<33>> must be placed at site P186.
   Place IOB IRF_DOUT<33> in site P186.
Resolved that IOB <IRF_DOUT<34>> must be placed at site P187.
   Place IOB IRF_DOUT<34> in site P187.
Resolved that IOB <IRF_DOUT<35>> must be placed at site P188.
   Place IOB IRF_DOUT<35> in site P188.
Resolved that IOB <IRF_DOUT<3>> must be placed at site P117.
   Place IOB IRF_DOUT<3> in site P117.
Resolved that IOB <IRF_DOUT<4>> must be placed at site P118.
   Place IOB IRF_DOUT<4> in site P118.
Resolved that IOB <IRF_DOUT<5>> must be placed at site P124.
   Place IOB IRF_DOUT<5> in site P124.
Resolved that IOB <IRF_DOUT<6>> must be placed at site P125.
   Place IOB IRF_DOUT<6> in site P125.
Resolved that IOB <IRF_DOUT<7>> must be placed at site P126.
   Place IOB IRF_DOUT<7> in site P126.
Resolved that IOB <IRF_DOUT<8>> must be placed at site P127.
   Place IOB IRF_DOUT<8> in site P127.
Resolved that IOB <IRF_DOUT<9>> must be placed at site P128.
   Place IOB IRF_DOUT<9> in site P128.
Resolved that IOB <IRF_RD> must be placed at site P154.
   Place IOB IRF_RD in site P154.
Resolved that IOB <IRF_ST> must be placed at site P156.
   Place IOB IRF_ST in site P156.
Resolved that IOB <IWF_AF> must be placed at site P159.
   Place IOB IWF_AF in site P159.
Resolved that IOB <IWF_DIN<0>> must be placed at site P113.
   Place IOB IWF_DIN<0> in site P113.
Resolved that IOB <IWF_DIN<10>> must be placed at site P102.
   Place IOB IWF_DIN<10> in site P102.
Resolved that IOB <IWF_DIN<11>> must be placed at site P100.
   Place IOB IWF_DIN<11> in site P100.
Resolved that IOB <IWF_DIN<12>> must be placed at site P99.
   Place IOB IWF_DIN<12> in site P99.
Resolved that IOB <IWF_DIN<13>> must be placed at site P97.
   Place IOB IWF_DIN<13> in site P97.
Resolved that IOB <IWF_DIN<14>> must be placed at site P96.
   Place IOB IWF_DIN<14> in site P96.
Resolved that IOB <IWF_DIN<15>> must be placed at site P95.
   Place IOB IWF_DIN<15> in site P95.
Resolved that IOB <IWF_DIN<16>> must be placed at site P208.
   Place IOB IWF_DIN<16> in site P208.
Resolved that IOB <IWF_DIN<17>> must be placed at site P207.
   Place IOB IWF_DIN<17> in site P207.
Resolved that IOB <IWF_DIN<18>> must be placed at site P206.
   Place IOB IWF_DIN<18> in site P206.
Resolved that IOB <IWF_DIN<19>> must be placed at site P205.
   Place IOB IWF_DIN<19> in site P205.
Resolved that IOB <IWF_DIN<1>> must be placed at site P112.
   Place IOB IWF_DIN<1> in site P112.
Resolved that IOB <IWF_DIN<20>> must be placed at site P203.
   Place IOB IWF_DIN<20> in site P203.
Resolved that IOB <IWF_DIN<21>> must be placed at site P202.
   Place IOB IWF_DIN<21> in site P202.
Resolved that IOB <IWF_DIN<22>> must be placed at site P200.
   Place IOB IWF_DIN<22> in site P200.
Resolved that IOB <IWF_DIN<23>> must be placed at site P199.
   Place IOB IWF_DIN<23> in site P199.
Resolved that IOB <IWF_DIN<24>> must be placed at site P198.
   Place IOB IWF_DIN<24> in site P198.
Resolved that IOB <IWF_DIN<25>> must be placed at site P197.
   Place IOB IWF_DIN<25> in site P197.
Resolved that IOB <IWF_DIN<26>> must be placed at site P194.
   Place IOB IWF_DIN<26> in site P194.
Resolved that IOB <IWF_DIN<27>> must be placed at site P193.
   Place IOB IWF_DIN<27> in site P193.
Resolved that IOB <IWF_DIN<28>> must be placed at site P192.
   Place IOB IWF_DIN<28> in site P192.
Resolved that IOB <IWF_DIN<29>> must be placed at site P191.
   Place IOB IWF_DIN<29> in site P191.
Resolved that IOB <IWF_DIN<2>> must be placed at site P111.
   Place IOB IWF_DIN<2> in site P111.
Resolved that IOB <IWF_DIN<30>> must be placed at site P190.
   Place IOB IWF_DIN<30> in site P190.
Resolved that IOB <IWF_DIN<31>> must be placed at site P189.
   Place IOB IWF_DIN<31> in site P189.
Resolved that IOB <IWF_DIN<3>> must be placed at site P110.
   Place IOB IWF_DIN<3> in site P110.
Resolved that IOB <IWF_DIN<4>> must be placed at site P109.
   Place IOB IWF_DIN<4> in site P109.
Resolved that IOB <IWF_DIN<5>> must be placed at site P108.
   Place IOB IWF_DIN<5> in site P108.
Resolved that IOB <IWF_DIN<6>> must be placed at site P107.
   Place IOB IWF_DIN<6> in site P107.
Resolved that IOB <IWF_DIN<7>> must be placed at site P105.
   Place IOB IWF_DIN<7> in site P105.
Resolved that IOB <IWF_DIN<8>> must be placed at site P104.
   Place IOB IWF_DIN<8> in site P104.
Resolved that IOB <IWF_DIN<9>> must be placed at site P103.
   Place IOB IWF_DIN<9> in site P103.
Resolved that IOB <IWF_LD> must be placed at site P160.
   Place IOB IWF_LD in site P160.
Resolved that IOB <IWF_WR> must be placed at site P157.
   Place IOB IWF_WR in site P157.
Resolved that IOB <LDIN<10>> must be placed at site P86.
   Place IOB LDIN<10> in site P86.
Resolved that IOB <LDIN<11>> must be placed at site P87.
   Place IOB LDIN<11> in site P87.
Resolved that IOB <LDIN<12>> must be placed at site P88.
   Place IOB LDIN<12> in site P88.
Resolved that IOB <LDIN<13>> must be placed at site P92.
   Place IOB LDIN<13> in site P92.
Resolved that IOB <LDIN<14>> must be placed at site P93.
   Place IOB LDIN<14> in site P93.
Resolved that IOB <LDIN<15>> must be placed at site P94.
   Place IOB LDIN<15> in site P94.
Resolved that IOB <LDIN<16>> must be placed at site P209.
   Place IOB LDIN<16> in site P209.
Resolved that IOB <LDIN<17>> must be placed at site P210.
   Place IOB LDIN<17> in site P210.
Resolved that IOB <LDIN<18>> must be placed at site P213.
   Place IOB LDIN<18> in site P213.
Resolved that IOB <LDIN<19>> must be placed at site P214.
   Place IOB LDIN<19> in site P214.
Resolved that IOB <LDIN<20>> must be placed at site P215.
   Place IOB LDIN<20> in site P215.
Resolved that IOB <LDIN<21>> must be placed at site P216.
   Place IOB LDIN<21> in site P216.
Resolved that IOB <LDIN<22>> must be placed at site P217.
   Place IOB LDIN<22> in site P217.
Resolved that IOB <LDIN<23>> must be placed at site P218.
   Place IOB LDIN<23> in site P218.
Resolved that IOB <LDIN<24>> must be placed at site P220.
   Place IOB LDIN<24> in site P220.
Resolved that IOB <LDIN<25>> must be placed at site P221.
   Place IOB LDIN<25> in site P221.
Resolved that IOB <LDIN<26>> must be placed at site P223.
   Place IOB LDIN<26> in site P223.
Resolved that IOB <LDIN<27>> must be placed at site P225.
   Place IOB LDIN<27> in site P225.
Resolved that IOB <LDIN<2>> must be placed at site P73.
   Place IOB LDIN<2> in site P73.
Resolved that IOB <LDIN<3>> must be placed at site P74.
   Place IOB LDIN<3> in site P74.
Resolved that IOB <LDIN<4>> must be placed at site P77.
   Place IOB LDIN<4> in site P77.
Resolved that IOB <LDIN<5>> must be placed at site P79.
   Place IOB LDIN<5> in site P79.
Resolved that IOB <LDIN<6>> must be placed at site P81.
   Place IOB LDIN<6> in site P81.
Resolved that IOB <LDIN<7>> must be placed at site P82.
   Place IOB LDIN<7> in site P82.
Resolved that IOB <LDIN<8>> must be placed at site P84.
   Place IOB LDIN<8> in site P84.
Resolved that IOB <LDIN<9>> must be placed at site P85.
   Place IOB LDIN<9> in site P85.
Resolved that IOB <PAR> must be placed at site P33.
   Place IOB PAR in site P33.
Resolved that CLB <PCI_CORE/PCI_LC/OE_ADI> must be placed at site CLB_R9C2.
   Place CLB PCI_CORE/PCI_LC/OE_ADI in site CLB_R9C2.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/OE_LB> must be
placed at site CLB_R17C1.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/OE_LB in site CLB_R17C1.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CBE/IO1/OUT> must be placed at site
CLB_R19C1.
   Place CLB PCI_CORE/PCI_LC/PCI-CBE/IO1/OUT in site CLB_R19C1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T0> must be placed at site
TBUF_R27C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T0 in site TBUF_R27C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T1> must be placed at site
TBUF_R27C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T1 in site TBUF_R27C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T10> must be placed at site
TBUF_R22C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T10 in site TBUF_R22C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T11> must be placed at site
TBUF_R22C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T11 in site TBUF_R22C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T12> must be placed at site
TBUF_R21C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T12 in site TBUF_R21C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T13> must be placed at site
TBUF_R21C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T13 in site TBUF_R21C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T14> must be placed at site
TBUF_R20C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T14 in site TBUF_R20C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T15> must be placed at site
TBUF_R20C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T15 in site TBUF_R20C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T2> must be placed at site
TBUF_R26C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T2 in site TBUF_R26C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T3> must be placed at site
TBUF_R26C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T3 in site TBUF_R26C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T4> must be placed at site
TBUF_R25C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T4 in site TBUF_R25C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T5> must be placed at site
TBUF_R25C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T5 in site TBUF_R25C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T6> must be placed at site
TBUF_R24C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T6 in site TBUF_R24C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T7> must be placed at site
TBUF_R24C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T7 in site TBUF_R24C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T8> must be placed at site
TBUF_R23C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T8 in site TBUF_R23C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/LOWER/T9> must be placed at site
TBUF_R23C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/LOWER/T9 in site TBUF_R23C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T0> must be placed at site
TBUF_R9C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T0 in site TBUF_R9C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T1> must be placed at site
TBUF_R9C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T1 in site TBUF_R9C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T10> must be placed at site
TBUF_R4C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T10 in site TBUF_R4C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T11> must be placed at site
TBUF_R4C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T11 in site TBUF_R4C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T12> must be placed at site
TBUF_R3C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T12 in site TBUF_R3C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T13> must be placed at site
TBUF_R3C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T13 in site TBUF_R3C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T14> must be placed at site
TBUF_R2C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T14 in site TBUF_R2C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T15> must be placed at site
TBUF_R2C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T15 in site TBUF_R2C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T2> must be placed at site
TBUF_R8C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T2 in site TBUF_R8C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T3> must be placed at site
TBUF_R8C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T3 in site TBUF_R8C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T4> must be placed at site
TBUF_R7C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T4 in site TBUF_R7C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T5> must be placed at site
TBUF_R7C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T5 in site TBUF_R7C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T6> must be placed at site
TBUF_R6C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T6 in site TBUF_R6C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T7> must be placed at site
TBUF_R6C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T7 in site TBUF_R6C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T8> must be placed at site
TBUF_R5C7.2.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T8 in site TBUF_R5C7.2.
Resolved that TBUF <PCI_CORE/PCI_LC/0/UPPER/T9> must be placed at site
TBUF_R5C7.1.
   Place TBUF PCI_CORE/PCI_LC/0/UPPER/T9 in site TBUF_R5C7.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T0> must be placed at site
TBUF_R27C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T0 in site TBUF_R27C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T1> must be placed at site
TBUF_R27C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T1 in site TBUF_R27C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T10> must be placed at site
TBUF_R22C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T10 in site TBUF_R22C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T11> must be placed at site
TBUF_R22C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T11 in site TBUF_R22C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T12> must be placed at site
TBUF_R21C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T12 in site TBUF_R21C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T13> must be placed at site
TBUF_R21C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T13 in site TBUF_R21C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T14> must be placed at site
TBUF_R20C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T14 in site TBUF_R20C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T15> must be placed at site
TBUF_R20C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T15 in site TBUF_R20C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T2> must be placed at site
TBUF_R26C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T2 in site TBUF_R26C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T3> must be placed at site
TBUF_R26C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T3 in site TBUF_R26C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T4> must be placed at site
TBUF_R25C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T4 in site TBUF_R25C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T5> must be placed at site
TBUF_R25C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T5 in site TBUF_R25C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T6> must be placed at site
TBUF_R24C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T6 in site TBUF_R24C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T7> must be placed at site
TBUF_R24C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T7 in site TBUF_R24C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T8> must be placed at site
TBUF_R23C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T8 in site TBUF_R23C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/LOWER/T9> must be placed at site
TBUF_R23C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/LOWER/T9 in site TBUF_R23C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T0> must be placed at site
TBUF_R9C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T0 in site TBUF_R9C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T1> must be placed at site
TBUF_R9C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T1 in site TBUF_R9C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T10> must be placed at site
TBUF_R4C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T10 in site TBUF_R4C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T11> must be placed at site
TBUF_R4C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T11 in site TBUF_R4C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T12> must be placed at site
TBUF_R3C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T12 in site TBUF_R3C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T13> must be placed at site
TBUF_R3C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T13 in site TBUF_R3C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T14> must be placed at site
TBUF_R2C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T14 in site TBUF_R2C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T15> must be placed at site
TBUF_R2C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T15 in site TBUF_R2C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T2> must be placed at site
TBUF_R8C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T2 in site TBUF_R8C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T3> must be placed at site
TBUF_R8C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T3 in site TBUF_R8C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T4> must be placed at site
TBUF_R7C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T4 in site TBUF_R7C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T5> must be placed at site
TBUF_R7C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T5 in site TBUF_R7C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T6> must be placed at site
TBUF_R6C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T6 in site TBUF_R6C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T7> must be placed at site
TBUF_R6C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T7 in site TBUF_R6C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T8> must be placed at site
TBUF_R5C6.2.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T8 in site TBUF_R5C6.2.
Resolved that TBUF <PCI_CORE/PCI_LC/1/UPPER/T9> must be placed at site
TBUF_R5C6.1.
   Place TBUF PCI_CORE/PCI_LC/1/UPPER/T9 in site TBUF_R5C6.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T0> must be placed at site
TBUF_R27C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T0 in site TBUF_R27C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T1> must be placed at site
TBUF_R27C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T1 in site TBUF_R27C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T10> must be placed at site
TBUF_R22C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T10 in site TBUF_R22C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T11> must be placed at site
TBUF_R22C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T11 in site TBUF_R22C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T12> must be placed at site
TBUF_R21C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T12 in site TBUF_R21C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T13> must be placed at site
TBUF_R21C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T13 in site TBUF_R21C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T14> must be placed at site
TBUF_R20C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T14 in site TBUF_R20C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T15> must be placed at site
TBUF_R20C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T15 in site TBUF_R20C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T2> must be placed at site
TBUF_R26C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T2 in site TBUF_R26C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T3> must be placed at site
TBUF_R26C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T3 in site TBUF_R26C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T4> must be placed at site
TBUF_R25C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T4 in site TBUF_R25C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T5> must be placed at site
TBUF_R25C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T5 in site TBUF_R25C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T6> must be placed at site
TBUF_R24C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T6 in site TBUF_R24C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T7> must be placed at site
TBUF_R24C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T7 in site TBUF_R24C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T8> must be placed at site
TBUF_R23C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T8 in site TBUF_R23C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/LOWER/T9> must be placed at site
TBUF_R23C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/LOWER/T9 in site TBUF_R23C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T0> must be placed at site
TBUF_R9C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T0 in site TBUF_R9C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T1> must be placed at site
TBUF_R9C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T1 in site TBUF_R9C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T10> must be placed at site
TBUF_R4C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T10 in site TBUF_R4C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T11> must be placed at site
TBUF_R4C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T11 in site TBUF_R4C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T12> must be placed at site
TBUF_R3C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T12 in site TBUF_R3C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T13> must be placed at site
TBUF_R3C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T13 in site TBUF_R3C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T14> must be placed at site
TBUF_R2C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T14 in site TBUF_R2C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T15> must be placed at site
TBUF_R2C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T15 in site TBUF_R2C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T2> must be placed at site
TBUF_R8C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T2 in site TBUF_R8C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T3> must be placed at site
TBUF_R8C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T3 in site TBUF_R8C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T4> must be placed at site
TBUF_R7C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T4 in site TBUF_R7C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T5> must be placed at site
TBUF_R7C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T5 in site TBUF_R7C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T6> must be placed at site
TBUF_R6C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T6 in site TBUF_R6C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T7> must be placed at site
TBUF_R6C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T7 in site TBUF_R6C2.1.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T8> must be placed at site
TBUF_R5C2.2.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T8 in site TBUF_R5C2.2.
Resolved that TBUF <PCI_CORE/PCI_LC/4/UPPER/T9> must be placed at site
TBUF_R5C2.1.
   Place TBUF PCI_CORE/PCI_LC/4/UPPER/T9 in site TBUF_R5C2.1.
Resolved that CLB <PCI_CORE/PCI_LC/BAR0/NS_EQ> must be placed at site
CLB_R14C6.
   Place CLB PCI_CORE/PCI_LC/BAR0/NS_EQ in site CLB_R14C6.
Resolved that CLB <PCI_CORE/PCI_LC/BAR1/NS_EQ> must be placed at site
CLB_R15C6.
   Place CLB PCI_CORE/PCI_LC/BAR1/NS_EQ in site CLB_R15C6.
Resolved that CLB <PCI_CORE/PCI_LC/BAR2/NS_EQ> must be placed at site
CLB_R17C7.
   Place CLB PCI_CORE/PCI_LC/BAR2/NS_EQ in site CLB_R17C7.
Resolved that CLB <PCI_CORE/PCI_LC/DATA_VLD/NS_MDV> must be placed at site
CLB_R12C2.
   Place CLB PCI_CORE/PCI_LC/DATA_VLD/NS_MDV in site CLB_R12C2.
Resolved that CLB <M_DATA_VLD> must be placed at site CLB_R12C10.
   Place CLB M_DATA_VLD in site CLB_R12C10.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T0> must be placed at site
TBUF_R27C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T0 in site TBUF_R27C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T1> must be placed at site
TBUF_R27C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T1 in site TBUF_R27C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T10> must be placed at site
TBUF_R22C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T10 in site TBUF_R22C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T11> must be placed at site
TBUF_R22C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T11 in site TBUF_R22C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T12> must be placed at site
TBUF_R21C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T12 in site TBUF_R21C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T13> must be placed at site
TBUF_R21C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T13 in site TBUF_R21C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T14> must be placed at site
TBUF_R20C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T14 in site TBUF_R20C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T15> must be placed at site
TBUF_R20C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T15 in site TBUF_R20C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T2> must be placed at site
TBUF_R26C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T2 in site TBUF_R26C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T3> must be placed at site
TBUF_R26C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T3 in site TBUF_R26C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T4> must be placed at site
TBUF_R25C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T4 in site TBUF_R25C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T5> must be placed at site
TBUF_R25C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T5 in site TBUF_R25C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T6> must be placed at site
TBUF_R24C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T6 in site TBUF_R24C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T7> must be placed at site
TBUF_R24C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T7 in site TBUF_R24C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T8> must be placed at site
TBUF_R23C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T8 in site TBUF_R23C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/LOWER/T9> must be placed at site
TBUF_R23C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/LOWER/T9 in site TBUF_R23C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T0> must be placed at site
TBUF_R9C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T0 in site TBUF_R9C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T1> must be placed at site
TBUF_R9C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T1 in site TBUF_R9C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T10> must be placed at site
TBUF_R4C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T10 in site TBUF_R4C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T11> must be placed at site
TBUF_R4C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T11 in site TBUF_R4C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T12> must be placed at site
TBUF_R3C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T12 in site TBUF_R3C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T13> must be placed at site
TBUF_R3C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T13 in site TBUF_R3C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T14> must be placed at site
TBUF_R2C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T14 in site TBUF_R2C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T15> must be placed at site
TBUF_R2C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T15 in site TBUF_R2C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T2> must be placed at site
TBUF_R8C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T2 in site TBUF_R8C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T3> must be placed at site
TBUF_R8C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T3 in site TBUF_R8C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T4> must be placed at site
TBUF_R7C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T4 in site TBUF_R7C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T5> must be placed at site
TBUF_R7C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T5 in site TBUF_R7C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T6> must be placed at site
TBUF_R6C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T6 in site TBUF_R6C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T7> must be placed at site
TBUF_R6C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T7 in site TBUF_R6C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T8> must be placed at site
TBUF_R5C3.2.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T8 in site TBUF_R5C3.2.
Resolved that TBUF <PCI_CORE/PCI_LC/E/UPPER/T9> must be placed at site
TBUF_R5C3.1.
   Place TBUF PCI_CORE/PCI_LC/E/UPPER/T9 in site TBUF_R5C3.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T0> must be placed at site
TBUF_R27C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T0 in site TBUF_R27C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T1> must be placed at site
TBUF_R27C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T1 in site TBUF_R27C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T10> must be placed at site
TBUF_R22C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T10 in site TBUF_R22C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T11> must be placed at site
TBUF_R22C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T11 in site TBUF_R22C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T12> must be placed at site
TBUF_R21C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T12 in site TBUF_R21C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T13> must be placed at site
TBUF_R21C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T13 in site TBUF_R21C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T14> must be placed at site
TBUF_R20C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T14 in site TBUF_R20C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T15> must be placed at site
TBUF_R20C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T15 in site TBUF_R20C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T2> must be placed at site
TBUF_R26C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T2 in site TBUF_R26C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T3> must be placed at site
TBUF_R26C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T3 in site TBUF_R26C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T4> must be placed at site
TBUF_R25C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T4 in site TBUF_R25C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T5> must be placed at site
TBUF_R25C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T5 in site TBUF_R25C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T6> must be placed at site
TBUF_R24C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T6 in site TBUF_R24C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T7> must be placed at site
TBUF_R24C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T7 in site TBUF_R24C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T8> must be placed at site
TBUF_R23C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T8 in site TBUF_R23C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/LOWER/T9> must be placed at site
TBUF_R23C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/LOWER/T9 in site TBUF_R23C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T0> must be placed at site
TBUF_R9C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T0 in site TBUF_R9C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T1> must be placed at site
TBUF_R9C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T1 in site TBUF_R9C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T10> must be placed at site
TBUF_R4C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T10 in site TBUF_R4C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T11> must be placed at site
TBUF_R4C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T11 in site TBUF_R4C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T12> must be placed at site
TBUF_R3C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T12 in site TBUF_R3C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T13> must be placed at site
TBUF_R3C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T13 in site TBUF_R3C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T14> must be placed at site
TBUF_R2C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T14 in site TBUF_R2C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T15> must be placed at site
TBUF_R2C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T15 in site TBUF_R2C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T2> must be placed at site
TBUF_R8C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T2 in site TBUF_R8C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T3> must be placed at site
TBUF_R8C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T3 in site TBUF_R8C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T4> must be placed at site
TBUF_R7C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T4 in site TBUF_R7C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T5> must be placed at site
TBUF_R7C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T5 in site TBUF_R7C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T6> must be placed at site
TBUF_R6C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T6 in site TBUF_R6C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T7> must be placed at site
TBUF_R6C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T7 in site TBUF_R6C8.1.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T8> must be placed at site
TBUF_R5C8.2.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T8 in site TBUF_R5C8.2.
Resolved that TBUF <PCI_CORE/PCI_LC/F/UPPER/T9> must be placed at site
TBUF_R5C8.1.
   Place TBUF PCI_CORE/PCI_LC/F/UPPER/T9 in site TBUF_R5C8.1.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/GNT_D_I-> must be placed at
site CLB_R11C3.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/GNT_D_I- in site CLB_R11C3.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/M_ADDR_LIVE> must be placed
at site CLB_R15C2.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/M_ADDR_LIVE in site CLB_R15C2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T0> must be placed
at site TBUF_R27C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T0 in site TBUF_R27C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T1> must be placed
at site TBUF_R27C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T1 in site TBUF_R27C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T10> must be placed
at site TBUF_R22C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T10 in site TBUF_R22C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T11> must be placed
at site TBUF_R22C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T11 in site TBUF_R22C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T12> must be placed
at site TBUF_R21C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T12 in site TBUF_R21C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T13> must be placed
at site TBUF_R21C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T13 in site TBUF_R21C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T14> must be placed
at site TBUF_R20C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T14 in site TBUF_R20C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T15> must be placed
at site TBUF_R20C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T15 in site TBUF_R20C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T2> must be placed
at site TBUF_R26C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T2 in site TBUF_R26C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T3> must be placed
at site TBUF_R26C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T3 in site TBUF_R26C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T4> must be placed
at site TBUF_R25C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T4 in site TBUF_R25C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T5> must be placed
at site TBUF_R25C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T5 in site TBUF_R25C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T6> must be placed
at site TBUF_R24C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T6 in site TBUF_R24C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T7> must be placed
at site TBUF_R24C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T7 in site TBUF_R24C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T8> must be placed
at site TBUF_R23C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T8 in site TBUF_R23C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T9> must be placed
at site TBUF_R23C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/LOWER/T9 in site TBUF_R23C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T0> must be placed
at site TBUF_R9C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T0 in site TBUF_R9C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T1> must be placed
at site TBUF_R9C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T1 in site TBUF_R9C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T10> must be placed
at site TBUF_R4C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T10 in site TBUF_R4C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T11> must be placed
at site TBUF_R4C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T11 in site TBUF_R4C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T12> must be placed
at site TBUF_R3C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T12 in site TBUF_R3C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T13> must be placed
at site TBUF_R3C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T13 in site TBUF_R3C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T14> must be placed
at site TBUF_R2C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T14 in site TBUF_R2C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T15> must be placed
at site TBUF_R2C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T15 in site TBUF_R2C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T2> must be placed
at site TBUF_R8C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T2 in site TBUF_R8C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T3> must be placed
at site TBUF_R8C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T3 in site TBUF_R8C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T4> must be placed
at site TBUF_R7C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T4 in site TBUF_R7C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T5> must be placed
at site TBUF_R7C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T5 in site TBUF_R7C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T6> must be placed
at site TBUF_R6C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T6 in site TBUF_R6C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T7> must be placed
at site TBUF_R6C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T7 in site TBUF_R6C9.1.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T8> must be placed
at site TBUF_R5C9.2.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T8 in site TBUF_R5C9.2.
Resolved that TBUF <PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T9> must be placed
at site TBUF_R5C9.1.
   Place TBUF PCI_CORE/PCI_LC/INITIATOR_CNTL/3/UPPER/T9 in site TBUF_R5C9.1.
Resolved that CLB <PCI_CORE/PCI_LC/TSTOP-> must be placed at site CLB_R15C4.
   Place CLB PCI_CORE/PCI_LC/TSTOP- in site CLB_R15C4.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/DR_BUS/DR_BUS> must be placed
at site CLB_R10C5.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/DR_BUS/DR_BUS in site CLB_R10C5.
Resolved that CLB <PCI_CORE/PCI_LC/NS_FRAME-> must be placed at site CLB_R11C4.
   Place CLB PCI_CORE/PCI_LC/NS_FRAME- in site CLB_R11C4.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/EOT_LIVE> must be
placed at site CLB_R12C3.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/EOT_LIVE in site
CLB_R12C3.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/IRDY/NS> must be placed at
site CLB_R13C1.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/IRDY/NS in site CLB_R13C1.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/I_IDLE/I_IDLE> must be placed
at site CLB_R10C4.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/I_IDLE/I_IDLE in site CLB_R10C4.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/I_IDLE/MDATA_AND_DRBUS> must
be placed at site CLB_R9C4.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/I_IDLE/MDATA_AND_DRBUS in site
CLB_R9C4.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/M_DATA/MDATA> must be placed
at site CLB_R13C6.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/M_DATA/MDATA in site CLB_R13C6.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/START_AD> must be
placed at site CLB_R13C4.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/START_AD in site
CLB_R13C4.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/NS> must be placed
at site CLB_R12C1.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/NS in site CLB_R12C1.
Resolved that CLB <PCI_CORE/PCI_LC/EOT> must be placed at site CLB_R10C2.
   Place CLB PCI_CORE/PCI_LC/EOT in site CLB_R10C2.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/FSLOT> must be
placed at site CLB_R11C1.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME/FSLOT in site CLB_R11C1.
Resolved that CLB <PCI_CORE/PCI_LC/OE_FRAME> must be placed at site CLB_R10C3.
   Place CLB PCI_CORE/PCI_LC/OE_FRAME in site CLB_R10C3.
Resolved that CLB <PCI_CORE/PCI_LC/INITIATOR_CNTL/S_TAR/NS_S_TAR> must be
placed at site CLB_R12C4.
   Place CLB PCI_CORE/PCI_LC/INITIATOR_CNTL/S_TAR/NS_S_TAR in site CLB_R12C4.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/PERR> must be placed at site
CLB_R16C1.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/PERR in site CLB_R16C1.
Resolved that CLB <PCI_CORE/PCI_LC/OUT_CE/ZERO_CE_T> must be placed at site
CLB_R11C2.
   Place CLB PCI_CORE/PCI_LC/OUT_CE/ZERO_CE_T in site CLB_R11C2.
Resolved that CLB <PCI_CORE/PCI_LC/OUT_CE/FIRST> must be placed at site
CLB_R16C3.
   Place CLB PCI_CORE/PCI_LC/OUT_CE/FIRST in site CLB_R16C3.
Resolved that CLB <PCI_CORE/PCI_LC/OUT_CE/ZERO_CE_B> must be placed at site
CLB_R17C2.
   Place CLB PCI_CORE/PCI_LC/OUT_CE/ZERO_CE_B in site CLB_R17C2.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/PAR> must be placed at site
CLB_R15C3.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/PAR in site CLB_R15C3.
Resolved that CLB <PCI_CORE/PCI_LC/OUT_SEL/OUT_SEL> must be placed at site
CLB_R16C2.
   Place CLB PCI_CORE/PCI_LC/OUT_SEL/OUT_SEL in site CLB_R16C2.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT0> must be placed at site CLB_R27C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT0 in site CLB_R27C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO0/OUT> must be placed at site
CLB_R17C9.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO0/OUT in site CLB_R17C9.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO1/OUT> must be placed at site
CLB_R17C8.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO1/OUT in site CLB_R17C8.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT10> must be placed at site CLB_R22C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT10 in site CLB_R22C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO11/OUT> must be placed at site
CLB_R22C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO11/OUT in site CLB_R22C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT12> must be placed at site CLB_R21C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT12 in site CLB_R21C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO13/OUT> must be placed at site
CLB_R21C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO13/OUT in site CLB_R21C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT14> must be placed at site CLB_R20C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT14 in site CLB_R20C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO15/OUT> must be placed at site
CLB_R20C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO15/OUT in site CLB_R20C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT16> must be placed at site CLB_R9C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT16 in site CLB_R9C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO16/OUT> must be placed at site
CLB_R10C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO16/OUT in site CLB_R10C1.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO17/OUT> must be placed at site
CLB_R9C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO17/OUT in site CLB_R9C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT18> must be placed at site CLB_R8C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT18 in site CLB_R8C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO19/OUT> must be placed at site
CLB_R8C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO19/OUT in site CLB_R8C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT2> must be placed at site CLB_R26C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT2 in site CLB_R26C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO3/OUT> must be placed at site
CLB_R17C6.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO3/OUT in site CLB_R17C6.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT20> must be placed at site CLB_R7C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT20 in site CLB_R7C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO22/OUT> must be placed at site
CLB_R7C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO22/OUT in site CLB_R7C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT22> must be placed at site CLB_R6C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT22 in site CLB_R6C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO23/OUT> must be placed at site
CLB_R6C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO23/OUT in site CLB_R6C1.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT24> must be placed at site CLB_R5C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT24 in site CLB_R5C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO25/OUT> must be placed at site
CLB_R11C5.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO25/OUT in site CLB_R11C5.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT26> must be placed at site CLB_R4C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT26 in site CLB_R4C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO26/OUT> must be placed at site
CLB_R11C6.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO26/OUT in site CLB_R11C6.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT28> must be placed at site CLB_R3C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT28 in site CLB_R3C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO29/OUT> must be placed at site
CLB_R11C7.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO29/OUT in site CLB_R11C7.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT30> must be placed at site CLB_R2C5.
   Place CLB PCI_CORE/PCI_LC/ADOUT30 in site CLB_R2C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO30/OUT> must be placed at site
CLB_R11C8.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO30/OUT in site CLB_R11C8.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO31/OUT> must be placed at site
CLB_R11C9.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO31/OUT in site CLB_R11C9.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT4> must be placed at site CLB_R25C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT4 in site CLB_R25C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO4/OUT> must be placed at site
CLB_R17C5.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO4/OUT in site CLB_R17C5.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT6> must be placed at site CLB_R24C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT6 in site CLB_R24C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO6/OUT> must be placed at site
CLB_R17C3.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO6/OUT in site CLB_R17C3.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO7/OUT> must be placed at site
CLB_R18C2.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO7/OUT in site CLB_R18C2.
Resolved that CLB <PCI_CORE/PCI_LC/ADOUT8> must be placed at site CLB_R23C6.
   Place CLB PCI_CORE/PCI_LC/ADOUT8 in site CLB_R23C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-AD/IO9/OUT> must be placed at site
CLB_R23C1.
   Place CLB PCI_CORE/PCI_LC/PCI-AD/IO9/OUT in site CLB_R23C1.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/DSTR> must be placed at site
CLB_R12C5.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/DSTR in site CLB_R12C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/EN_CFGQ> must be placed at site
CLB_R16C5.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/EN_CFGQ in site CLB_R16C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/HIT> must be placed at
site CLB_R15C5.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/HIT in site CLB_R15C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-DSEL/NS> must be
placed at site CLB_R14C1.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-DSEL/NS in site CLB_R14C1.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-STOP/NS> must be
placed at site CLB_R14C2.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-STOP/NS in site CLB_R14C2.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/BUSY> must be
placed at site CLB_R14C5.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/BUSY in site CLB_R14C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/NS> must be
placed at site CLB_R13C2.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/NS in site CLB_R13C2.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/SWAN0> must be
placed at site CLB_R13C3.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/SWAN0 in site
CLB_R13C3.
Resolved that CLB <PCI_CORE/PCI_LC/OE_STOP> must be placed at site CLB_R14C3.
   Place CLB PCI_CORE/PCI_LC/OE_STOP in site CLB_R14C3.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_PERR_IN> must
be placed at site CLB_R14C4.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_PERR_IN in site
CLB_R14C4.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/TBEGIN> must be
placed at site CLB_R13C5.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/TBEGIN in site
CLB_R13C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_B> must be
placed at site CLB_R28C3.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_B in site CLB_R28C3.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_LB> must be
placed at site CLB_R23C2.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_LB in site CLB_R23C2.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_LT> must be
placed at site CLB_R5C2.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_LT in site CLB_R5C2.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_T> must be
placed at site CLB_R1C3.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_T in site CLB_R1C3.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY_IN> must
be placed at site CLB_R16C4.
   Place CLB PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-XOE/OE_TRDY_IN in site
CLB_R16C4.
Resolved that CLB <STATUS<22>> must be placed at site CLB_R6C6.
   Place CLB STATUS<22> in site CLB_R6C6.
Resolved that CLB <STATUS<27>> must be placed at site CLB_R4C6.
   Place CLB STATUS<27> in site CLB_R4C6.
Resolved that CLB <STATUS<29>> must be placed at site CLB_R3C6.
   Place CLB STATUS<29> in site CLB_R3C6.
Resolved that CLB <STATUS<30>> must be placed at site CLB_R2C6.
   Place CLB STATUS<30> in site CLB_R2C6.
Resolved that CLB <STATUS<24>> must be placed at site CLB_R5C6.
   Place CLB STATUS<24> in site CLB_R5C6.
Resolved that CLB <PCI_CORE/PCI_LC/BAR_START> must be placed at site CLB_R16C6.
   Place CLB PCI_CORE/PCI_LC/BAR_START in site CLB_R16C6.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/P0I> must be placed at site
CLB_R26C5.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/P0I in site CLB_R26C5.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/P3I> must be placed at site
CLB_R3C4.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/P3I in site CLB_R3C4.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/P1I> must be placed at site
CLB_R22C4.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/P1I in site CLB_R22C4.
Resolved that CLB <PCI_CORE/PCI_LC/PCI-PAR/P2I> must be placed at site
CLB_R7C2.
   Place CLB PCI_CORE/PCI_LC/PCI-PAR/P2I in site CLB_R7C2.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW0> must be placed at site CLB_R27C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW0 in site CLB_R27C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW10> must be placed at site CLB_R22C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW10 in site CLB_R22C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW12> must be placed at site CLB_R21C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW12 in site CLB_R21C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW14> must be placed at site CLB_R20C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW14 in site CLB_R20C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW2> must be placed at site CLB_R26C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW2 in site CLB_R26C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW4> must be placed at site CLB_R25C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW4 in site CLB_R25C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW6> must be placed at site CLB_R24C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW6 in site CLB_R24C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW8> must be placed at site CLB_R23C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW8 in site CLB_R23C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW16> must be placed at site CLB_R9C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW16 in site CLB_R9C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW26> must be placed at site CLB_R4C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW26 in site CLB_R4C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW28> must be placed at site CLB_R3C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW28 in site CLB_R3C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW30> must be placed at site CLB_R2C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW30 in site CLB_R2C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW18> must be placed at site CLB_R8C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW18 in site CLB_R8C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW20> must be placed at site CLB_R7C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW20 in site CLB_R7C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW22> must be placed at site CLB_R6C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW22 in site CLB_R6C10.
Resolved that CLB <PCI_CORE/PCI_LC/SHADOW24> must be placed at site CLB_R5C10.
   Place CLB PCI_CORE/PCI_LC/SHADOW24 in site CLB_R5C10.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T0> must be placed at site
TBUF_R27C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T0 in site TBUF_R27C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T1> must be placed at site
TBUF_R27C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T1 in site TBUF_R27C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T10> must be placed at site
TBUF_R22C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T10 in site TBUF_R22C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T11> must be placed at site
TBUF_R22C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T11 in site TBUF_R22C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T12> must be placed at site
TBUF_R21C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T12 in site TBUF_R21C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T13> must be placed at site
TBUF_R21C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T13 in site TBUF_R21C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T14> must be placed at site
TBUF_R20C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T14 in site TBUF_R20C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T15> must be placed at site
TBUF_R20C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T15 in site TBUF_R20C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T2> must be placed at site
TBUF_R26C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T2 in site TBUF_R26C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T3> must be placed at site
TBUF_R26C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T3 in site TBUF_R26C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T4> must be placed at site
TBUF_R25C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T4 in site TBUF_R25C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T5> must be placed at site
TBUF_R25C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T5 in site TBUF_R25C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T6> must be placed at site
TBUF_R24C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T6 in site TBUF_R24C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T7> must be placed at site
TBUF_R24C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T7 in site TBUF_R24C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T8> must be placed at site
TBUF_R23C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T8 in site TBUF_R23C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/LOWER/T9> must be placed at site
TBUF_R23C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/LOWER/T9 in site TBUF_R23C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T0> must be placed at site
TBUF_R9C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T0 in site TBUF_R9C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T1> must be placed at site
TBUF_R9C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T1 in site TBUF_R9C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T10> must be placed at site
TBUF_R4C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T10 in site TBUF_R4C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T11> must be placed at site
TBUF_R4C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T11 in site TBUF_R4C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T12> must be placed at site
TBUF_R3C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T12 in site TBUF_R3C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T13> must be placed at site
TBUF_R3C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T13 in site TBUF_R3C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T14> must be placed at site
TBUF_R2C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T14 in site TBUF_R2C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T15> must be placed at site
TBUF_R2C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T15 in site TBUF_R2C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T2> must be placed at site
TBUF_R8C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T2 in site TBUF_R8C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T3> must be placed at site
TBUF_R8C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T3 in site TBUF_R8C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T4> must be placed at site
TBUF_R7C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T4 in site TBUF_R7C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T5> must be placed at site
TBUF_R7C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T5 in site TBUF_R7C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T6> must be placed at site
TBUF_R6C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T6 in site TBUF_R6C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T7> must be placed at site
TBUF_R6C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T7 in site TBUF_R6C1.1.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T8> must be placed at site
TBUF_R5C1.2.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T8 in site TBUF_R5C1.2.
Resolved that TBUF <PCI_CORE/PCI_LC/X/UPPER/T9> must be placed at site
TBUF_R5C1.1.
   Place TBUF PCI_CORE/PCI_LC/X/UPPER/T9 in site TBUF_R5C1.1.
Resolved that CLKIOB <PCLK> must be placed at site P2.
   Place CLKIOB PCLK in site P2.
Resolved that IOB <PERR_N> must be placed at site P31.
   Place IOB PERR_N in site P31.
Resolved that IOB <REQ_N> must be placed at site P34.
   Place IOB REQ_N in site P34.
Resolved that IOB <RST_N> must be placed at site P123.
   Place IOB RST_N in site P123.
Resolved that IOB <SERR_N> must be placed at site P32.
   Place IOB SERR_N in site P32.
Resolved that IOB <STOP_N> must be placed at site P28.
   Place IOB STOP_N in site P28.
Resolved that IOB <TRDY_N> must be placed at site P26.
   Place IOB TRDY_N in site P26.
Resolved that CLB <VOY_INST/registers/addr_copy<6>> must be placed at site
CLB_R24C12.
   Place CLB VOY_INST/registers/addr_copy<6> in site CLB_R24C12.
Resolved that CLB <VOY_INST/registers/addr_shadow_Q469<8>> must be placed at
site CLB_R23C12.
   Place CLB VOY_INST/registers/addr_shadow_Q469<8> in site CLB_R23C12.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ml<2>> must be placed at
site CLB_R22C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ml<2> in site CLB_R22C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ml<4>> must be placed at
site CLB_R21C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ml<4> in site CLB_R21C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ml<6>> must be placed at
site CLB_R20C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ml<6> in site CLB_R20C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_mh<0>> must be placed at
site CLB_R9C15.
   Place CLB VOY_INST/registers/xfer_padri/input_mh<0> in site CLB_R9C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_mh<2>> must be placed at
site CLB_R8C15.
   Place CLB VOY_INST/registers/xfer_padri/input_mh<2> in site CLB_R8C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_mh<4>> must be placed at
site CLB_R7C15.
   Place CLB VOY_INST/registers/xfer_padri/input_mh<4> in site CLB_R7C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_mh<6>> must be placed at
site CLB_R6C15.
   Place CLB VOY_INST/registers/xfer_padri/input_mh<6> in site CLB_R6C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_hh<0>> must be placed at
site CLB_R5C15.
   Place CLB VOY_INST/registers/xfer_padri/input_hh<0> in site CLB_R5C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_hh<2>> must be placed at
site CLB_R4C15.
   Place CLB VOY_INST/registers/xfer_padri/input_hh<2> in site CLB_R4C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_hh<4>> must be placed at
site CLB_R3C15.
   Place CLB VOY_INST/registers/xfer_padri/input_hh<4> in site CLB_R3C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ll<2>> must be placed at
site CLB_R26C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ll<2> in site CLB_R26C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_hh<6>> must be placed at
site CLB_R2C15.
   Place CLB VOY_INST/registers/xfer_padri/input_hh<6> in site CLB_R2C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ll<4>> must be placed at
site CLB_R25C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ll<4> in site CLB_R25C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ll<6>> must be placed at
site CLB_R24C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ll<6> in site CLB_R24C15.
Resolved that CLB <VOY_INST/registers/xfer_padri/input_ml<0>> must be placed at
site CLB_R23C15.
   Place CLB VOY_INST/registers/xfer_padri/input_ml<0> in site CLB_R23C15.
Resolved that CLB <VOY_INST/la<2>> must be placed at site CLB_R26C25.
   Place CLB VOY_INST/la<2> in site CLB_R26C25.
Resolved that CLB <VOY_INST/la<12>> must be placed at site CLB_R22C26.
   Place CLB VOY_INST/la<12> in site CLB_R22C26.
Resolved that CLB <VOY_INST/la<13>> must be placed at site CLB_R21C26.
   Place CLB VOY_INST/la<13> in site CLB_R21C26.
Resolved that CLB <VOY_INST/la<14>> must be placed at site CLB_R20C25.
   Place CLB VOY_INST/la<14> in site CLB_R20C25.
Resolved that CLB <VOY_INST/la<15>> must be placed at site CLB_R20C26.
   Place CLB VOY_INST/la<15> in site CLB_R20C26.
Resolved that CLB <VOY_INST/la<4>> must be placed at site CLB_R25C25.
   Place CLB VOY_INST/la<4> in site CLB_R25C25.
Resolved that CLB <VOY_INST/la<6>> must be placed at site CLB_R24C25.
   Place CLB VOY_INST/la<6> in site CLB_R24C25.
Resolved that CLB <VOY_INST/la<8>> must be placed at site CLB_R23C25.
   Place CLB VOY_INST/la<8> in site CLB_R23C25.
Resolved that CLB <VOY_INST/la<9>> must be placed at site CLB_R23C26.
   Place CLB VOY_INST/la<9> in site CLB_R23C26.
Resolved that CLB <VOY_INST/la<10>> must be placed at site CLB_R22C25.
   Place CLB VOY_INST/la<10> in site CLB_R22C25.
Resolved that CLB <VOY_INST/la<11>> must be placed at site CLB_R21C25.
   Place CLB VOY_INST/la<11> in site CLB_R21C25.
Resolved that CLB <n1461> must be placed at site CLB_R27C27.
   Place CLB n1461 in site CLB_R27C27.
Resolved that CLB <n1451> must be placed at site CLB_R22C27.
   Place CLB n1451 in site CLB_R22C27.
Resolved that CLB <n1449> must be placed at site CLB_R21C27.
   Place CLB n1449 in site CLB_R21C27.
Resolved that CLB <n1447> must be placed at site CLB_R20C27.
   Place CLB n1447 in site CLB_R20C27.
Resolved that CLB <n1445> must be placed at site CLB_R9C27.
   Place CLB n1445 in site CLB_R9C27.
Resolved that CLB <n1443> must be placed at site CLB_R8C27.
   Place CLB n1443 in site CLB_R8C27.
Resolved that CLB <n1441> must be placed at site CLB_R7C27.
   Place CLB n1441 in site CLB_R7C27.
Resolved that CLB <n1439> must be placed at site CLB_R6C27.
   Place CLB n1439 in site CLB_R6C27.
Resolved that CLB <n1437> must be placed at site CLB_R5C27.
   Place CLB n1437 in site CLB_R5C27.
Resolved that CLB <n1435> must be placed at site CLB_R4C27.
   Place CLB n1435 in site CLB_R4C27.
Resolved that CLB <n1433> must be placed at site CLB_R3C27.
   Place CLB n1433 in site CLB_R3C27.
Resolved that CLB <n1459> must be placed at site CLB_R26C27.
   Place CLB n1459 in site CLB_R26C27.
Resolved that CLB <n1431> must be placed at site CLB_R2C27.
   Place CLB n1431 in site CLB_R2C27.
Resolved that CLB <n1457> must be placed at site CLB_R25C27.
   Place CLB n1457 in site CLB_R25C27.
Resolved that CLB <n1455> must be placed at site CLB_R24C27.
   Place CLB n1455 in site CLB_R24C27.
Resolved that CLB <n1453> must be placed at site CLB_R23C27.
   Place CLB n1453 in site CLB_R23C27.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<0>> must be placed at site
CLB_R27C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<0> in site CLB_R27C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<10>> must be placed at site
CLB_R22C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<10> in site CLB_R22C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<12>> must be placed at site
CLB_R21C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<12> in site CLB_R21C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<14>> must be placed at site
CLB_R20C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<14> in site CLB_R20C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<16>> must be placed at site
CLB_R9C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<16> in site CLB_R9C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<18>> must be placed at site
CLB_R8C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<18> in site CLB_R8C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<20>> must be placed at site
CLB_R7C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<20> in site CLB_R7C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<22>> must be placed at site
CLB_R6C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<22> in site CLB_R6C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<24>> must be placed at site
CLB_R5C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<24> in site CLB_R5C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<26>> must be placed at site
CLB_R4C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<26> in site CLB_R4C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<28>> must be placed at site
CLB_R3C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<28> in site CLB_R3C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<2>> must be placed at site
CLB_R26C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<2> in site CLB_R26C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<30>> must be placed at site
CLB_R2C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<30> in site CLB_R2C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<4>> must be placed at site
CLB_R25C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<4> in site CLB_R25C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<6>> must be placed at site
CLB_R24C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<6> in site CLB_R24C20.
Resolved that CLB <VOY_INST/transfer/iwf_din_dly<8>> must be placed at site
CLB_R23C20.
   Place CLB VOY_INST/transfer/iwf_din_dly<8> in site CLB_R23C20.
Resolved that CLB <VOY_INST/transfer/iwf_dout<0>> must be placed at site
CLB_R27C21.
   Place CLB VOY_INST/transfer/iwf_dout<0> in site CLB_R27C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<2>> must be placed at site
CLB_R26C21.
   Place CLB VOY_INST/transfer/iwf_dout<2> in site CLB_R26C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<4>> must be placed at site
CLB_R25C21.
   Place CLB VOY_INST/transfer/iwf_dout<4> in site CLB_R25C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<6>> must be placed at site
CLB_R24C21.
   Place CLB VOY_INST/transfer/iwf_dout<6> in site CLB_R24C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<8>> must be placed at site
CLB_R23C21.
   Place CLB VOY_INST/transfer/iwf_dout<8> in site CLB_R23C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<10>> must be placed at site
CLB_R22C21.
   Place CLB VOY_INST/transfer/iwf_dout<10> in site CLB_R22C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<12>> must be placed at site
CLB_R21C21.
   Place CLB VOY_INST/transfer/iwf_dout<12> in site CLB_R21C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<14>> must be placed at site
CLB_R20C21.
   Place CLB VOY_INST/transfer/iwf_dout<14> in site CLB_R20C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<16>> must be placed at site
CLB_R9C21.
   Place CLB VOY_INST/transfer/iwf_dout<16> in site CLB_R9C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<18>> must be placed at site
CLB_R8C21.
   Place CLB VOY_INST/transfer/iwf_dout<18> in site CLB_R8C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<20>> must be placed at site
CLB_R7C21.
   Place CLB VOY_INST/transfer/iwf_dout<20> in site CLB_R7C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<22>> must be placed at site
CLB_R6C21.
   Place CLB VOY_INST/transfer/iwf_dout<22> in site CLB_R6C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<24>> must be placed at site
CLB_R5C21.
   Place CLB VOY_INST/transfer/iwf_dout<24> in site CLB_R5C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<26>> must be placed at site
CLB_R4C21.
   Place CLB VOY_INST/transfer/iwf_dout<26> in site CLB_R4C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<28>> must be placed at site
CLB_R3C21.
   Place CLB VOY_INST/transfer/iwf_dout<28> in site CLB_R3C21.
Resolved that CLB <VOY_INST/transfer/iwf_dout<30>> must be placed at site
CLB_R2C21.
   Place CLB VOY_INST/transfer/iwf_dout<30> in site CLB_R2C21.
Resolved that CLB <n1411> must be placed at site CLB_R17C28.
   Place CLB n1411 in site CLB_R17C28.
Resolved that CLB <n1409> must be placed at site CLB_R16C28.
   Place CLB n1409 in site CLB_R16C28.
Resolved that CLB <n1407> must be placed at site CLB_R15C28.
   Place CLB n1407 in site CLB_R15C28.
Resolved that CLB <n1419> must be placed at site CLB_R21C28.
   Place CLB n1419 in site CLB_R21C28.
Resolved that CLB <n1417> must be placed at site CLB_R20C28.
   Place CLB n1417 in site CLB_R20C28.
Resolved that CLB <n1415> must be placed at site CLB_R19C28.
   Place CLB n1415 in site CLB_R19C28.
Resolved that CLB <n1413> must be placed at site CLB_R18C28.
   Place CLB n1413 in site CLB_R18C28.
Resolved that TBUF <VOY_INST/transfer/U1211> must be placed at site
TBUF_R3C21.1.
   Place TBUF VOY_INST/transfer/U1211 in site TBUF_R3C21.1.
Resolved that TBUF <VOY_INST/transfer/U1212> must be placed at site
TBUF_R2C21.2.
   Place TBUF VOY_INST/transfer/U1212 in site TBUF_R2C21.2.
Resolved that TBUF <VOY_INST/transfer/U1213> must be placed at site
TBUF_R25C21.1.
   Place TBUF VOY_INST/transfer/U1213 in site TBUF_R25C21.1.
Resolved that TBUF <VOY_INST/transfer/U1217> must be placed at site
TBUF_R21C21.1.
   Place TBUF VOY_INST/transfer/U1217 in site TBUF_R21C21.1.
Resolved that TBUF <VOY_INST/transfer/U1218> must be placed at site
TBUF_R7C21.2.
   Place TBUF VOY_INST/transfer/U1218 in site TBUF_R7C21.2.
Resolved that TBUF <VOY_INST/transfer/U1221> must be placed at site
TBUF_R27C21.1.
   Place TBUF VOY_INST/transfer/U1221 in site TBUF_R27C21.1.
Resolved that TBUF <VOY_INST/transfer/U1223> must be placed at site
TBUF_R9C21.1.
   Place TBUF VOY_INST/transfer/U1223 in site TBUF_R9C21.1.
Resolved that TBUF <VOY_INST/transfer/U1224> must be placed at site
TBUF_R5C21.2.
   Place TBUF VOY_INST/transfer/U1224 in site TBUF_R5C21.2.
Resolved that TBUF <VOY_INST/transfer/U1225> must be placed at site
TBUF_R23C21.2.
   Place TBUF VOY_INST/transfer/U1225 in site TBUF_R23C21.2.
Resolved that TBUF <VOY_INST/transfer/U1226> must be placed at site
TBUF_R20C21.1.
   Place TBUF VOY_INST/transfer/U1226 in site TBUF_R20C21.1.
Resolved that TBUF <VOY_INST/transfer/U1227> must be placed at site
TBUF_R4C21.2.
   Place TBUF VOY_INST/transfer/U1227 in site TBUF_R4C21.2.
Resolved that TBUF <VOY_INST/transfer/U1232> must be placed at site
TBUF_R26C21.1.
   Place TBUF VOY_INST/transfer/U1232 in site TBUF_R26C21.1.
Resolved that TBUF <VOY_INST/transfer/U1233> must be placed at site
TBUF_R22C21.1.
   Place TBUF VOY_INST/transfer/U1233 in site TBUF_R22C21.1.
Resolved that TBUF <VOY_INST/transfer/U1234> must be placed at site
TBUF_R6C21.2.
   Place TBUF VOY_INST/transfer/U1234 in site TBUF_R6C21.2.
Resolved that TBUF <VOY_INST/transfer/U1237> must be placed at site
TBUF_R24C21.1.
   Place TBUF VOY_INST/transfer/U1237 in site TBUF_R24C21.1.
Resolved that TBUF <VOY_INST/transfer/U1241> must be placed at site
TBUF_R8C21.2.
   Place TBUF VOY_INST/transfer/U1241 in site TBUF_R8C21.2.
Resolved that TBUF <VOY_INST/transfer/U1242> must be placed at site
TBUF_R22C21.2.
   Place TBUF VOY_INST/transfer/U1242 in site TBUF_R22C21.2.
Resolved that TBUF <VOY_INST/transfer/U1243> must be placed at site
TBUF_R6C21.1.
   Place TBUF VOY_INST/transfer/U1243 in site TBUF_R6C21.1.
Resolved that TBUF <VOY_INST/transfer/U1246> must be placed at site
TBUF_R24C21.2.
   Place TBUF VOY_INST/transfer/U1246 in site TBUF_R24C21.2.
Resolved that TBUF <VOY_INST/transfer/U1250> must be placed at site
TBUF_R8C21.1.
   Place TBUF VOY_INST/transfer/U1250 in site TBUF_R8C21.1.
Resolved that TBUF <VOY_INST/transfer/U1251> must be placed at site
TBUF_R20C21.2.
   Place TBUF VOY_INST/transfer/U1251 in site TBUF_R20C21.2.
Resolved that TBUF <VOY_INST/transfer/U1252> must be placed at site
TBUF_R4C21.1.
   Place TBUF VOY_INST/transfer/U1252 in site TBUF_R4C21.1.
Resolved that TBUF <VOY_INST/transfer/U1257> must be placed at site
TBUF_R26C21.2.
   Place TBUF VOY_INST/transfer/U1257 in site TBUF_R26C21.2.
Resolved that TBUF <VOY_INST/transfer/U1260> must be placed at site
TBUF_R27C21.2.
   Place TBUF VOY_INST/transfer/U1260 in site TBUF_R27C21.2.
Resolved that TBUF <VOY_INST/transfer/U1262> must be placed at site
TBUF_R9C21.2.
   Place TBUF VOY_INST/transfer/U1262 in site TBUF_R9C21.2.
Resolved that TBUF <VOY_INST/transfer/U1263> must be placed at site
TBUF_R5C21.1.
   Place TBUF VOY_INST/transfer/U1263 in site TBUF_R5C21.1.
Resolved that TBUF <VOY_INST/transfer/U1264> must be placed at site
TBUF_R23C21.1.
   Place TBUF VOY_INST/transfer/U1264 in site TBUF_R23C21.1.
Resolved that TBUF <VOY_INST/transfer/U1266> must be placed at site
TBUF_R2C21.1.
   Place TBUF VOY_INST/transfer/U1266 in site TBUF_R2C21.1.
Resolved that TBUF <VOY_INST/transfer/U1267> must be placed at site
TBUF_R3C21.2.
   Place TBUF VOY_INST/transfer/U1267 in site TBUF_R3C21.2.
Resolved that TBUF <VOY_INST/transfer/U1268> must be placed at site
TBUF_R25C21.2.
   Place TBUF VOY_INST/transfer/U1268 in site TBUF_R25C21.2.
Resolved that TBUF <VOY_INST/transfer/U1272> must be placed at site
TBUF_R21C21.2.
   Place TBUF VOY_INST/transfer/U1272 in site TBUF_R21C21.2.
Resolved that TBUF <VOY_INST/transfer/U1273> must be placed at site
TBUF_R7C21.1.
   Place TBUF VOY_INST/transfer/U1273 in site TBUF_R7C21.1.


Device utilization summary:

   Number of External IOBs           175 out of 192    91%
      Flops:                          43
      Latches:                         0
   Number of Global Buffer IOBs        1 out of 8      12%
      Flops:                           0
      Latches:                         0

   Number of CLBs                    741 out of 784    94%
      Total CLB Flops:               549 out of 1568   35%
      4 input LUTs:                  854 out of 1568   54%
      3 input LUTs:                  289 out of 784    36%

   Number of PRI-CLKs                  1 out of 4      25%
   Number of STARTUPs                  1 out of 1     100%
   Number of TBUFs                   320 out of 1680   19%



Overall effort level (-ol):   4 (set by user)
Placer effort level (-pl):    4 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    4 (default)
Timing method (-kpaths|-dfs): -kpaths (default)

Starting initial Timing Analysis.  REAL time: 11 secs 
Finished initial Timing Analysis.  REAL time: 20 secs 

Starting initial Placement phase.  REAL time: 24 secs 
Finished initial Placement phase.  REAL time: 25 secs 

Starting Constructive Placer.  REAL time: 26 secs 
Placer score = 1808104
Placer score = 1307644
Placer score = 1163977
Placer score = 1112996
Placer score = 1062971
Placer score = 1014188
Placer score = 997125
Placer score = 948907
Placer score = 924299
Placer score = 900954
Placer score = 866477
Placer score = 848940
Placer score = 826586
Placer score = 806411
Placer score = 803512
Placer score = 774435
Placer score = 750937
Placer score = 735818
Placer score = 705634
Placer score = 681281
Placer score = 667267
Placer score = 648916
Placer score = 636904
Placer score = 629883
Placer score = 592582
Placer score = 590196
Placer score = 573470
Placer score = 565610
Placer score = 561893
Placer score = 555773
Placer score = 548287
Placer score = 542619
Placer score = 536880
Placer score = 534964
Placer score = 534330
Placer score = 533384
Placer score = 533253
Placer score = 532631
Placer score = 530765
Placer score = 530341
Placer score = 530237
Placer score = 530039
Placer score = 530035
Finished Constructive Placer.  REAL time: 16 mins 48 secs 

Writing design to file "pci_top_fpr.ncd".

Starting Optimizing Placer.  REAL time: 16 mins 50 secs 
Optimizing  ...
Swapped 11 comps.
Xilinx Placer [1]   529763   REAL time: 17 mins 22 secs 

Optimizing  ..
Swapped 3 comps.
Xilinx Placer [2]   529763   REAL time: 17 mins 51 secs 

Finished Optimizing Placer.  REAL time: 17 mins 51 secs 

Writing design to file "pci_top_fpr.ncd".

Total REAL time to Placer completion: 17 mins 53 secs 
Total CPU time to Placer completion: 11 mins 51 secs 

0 connection(s) routed; 4900 unrouted active, 7 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 18 mins 36 secs 
Starting iterative routing. 
Routing active signals.
End of iteration 1 
4898 successful; 2 unrouted active,
   7 unrouted PWR/GND; (3040333) REAL time: 19 mins 50 secs 
End of iteration 2 
4900 successful; 0 unrouted active,
   7 unrouted PWR/GND; (91560) REAL time: 21 mins 40 secs 
Improving timing.
Routing PWR/GND nets.
Power and ground nets completely routed. 
End of iteration 3 
4907 successful; 0 unrouted; (13560) REAL time: 23 mins 35 secs 
End of iteration 4 
4907 successful; 0 unrouted; (0) REAL time: 24 mins 31 secs 
Constraints are met. 
Writing design to file "pci_top_fpr.ncd".
Starting cleanup 
Improving routing.
End of cleanup iteration 1 
4907 successful; 0 unrouted; (0) REAL time: 25 mins 47 secs 
Writing design to file "pci_top_fpr.ncd".
Starting delay cleanup 
Improving timing.
End of delay cleanup iteration 1 
4907 successful; 0 unrouted; (0) REAL time: 27 mins 17 secs 
Writing design to file "pci_top_fpr.ncd".
Total REAL time: 27 mins 19 secs 
Total CPU  time: 18 mins 45 secs 
End of route.  4907 routed (100.00%); 0 unrouted.
No errors found. 
The signal "PCI_CORE/PCI_LC/BAR2/NLMEM" has no loads so was not routed. 
The signal "PCI_CORE/PCI_LC/BAR2/BHIT" has no loads so was not routed. 
The signal "PCI_CORE/PCI_LC/BAR1/NLMEM" has no loads so was not routed. 
The signal "PCI_CORE/PCI_LC/BAR1/BHIT" has no loads so was not routed. 

Total REAL time to Router completion: 27 mins 22 secs 
Total CPU time to Router completion: 18 mins 48 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 508


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.905 ns
   The Average Connection Delay on critical nets is:       0.000 ns
   The Average Clock Skew for this design is:              0.109 ns
   The Maximum Pin Delay is:                              12.531 ns
   The Average Connection Delay on the 10 Worst Nets is:  10.912 ns

   Listing Pin Delays by value: (ns)

    d <= 10    < d <= 20   < d <= 30   < d <= 40   < d <= 50    d > 50
   ---------   ---------   ---------   ---------   ---------   ---------
        4601          18           0           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "PCLK" PERIOD =  30 nS   HIGH 50.000  | 30.000ns   | 29.437ns   | 5    
  %                                         |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Writing design to file "pci_top_fpr.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 27 mins 32 secs 
Total CPU time to PAR completion: 18 mins 58 secs 

PAR done.