--------------------------------------------------------------------------------
Xilinx TRACE, Version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Design file:              pci_top_fpr.ncd
Physical constraint file: pci_top.pcf
Device,speed:             xcs40,-4 (x1_0.14 1.6 PRELIMINARY)
Report level:             verbose report, limited to 1 item per constraint
--------------------------------------------------------------------------------


================================================================================
Timing constraint: NET "PCLK" PERIOD =  30 nS   HIGH 50.000 % ;
 26666 items analyzed, 0 timing errors detected.
 Minimum period is  29.437ns.
--------------------------------------------------------------------------------
Slack:     0.563ns path FRAME_N to PCI_CORE/PCI_LC/PCI-CNTL/DSTR relative to
          29.426ns total path delay
           0.011ns clock skew
          30.000ns delay constraint

Path FRAME_N to PCI_CORE/PCI_LC/PCI-CNTL/DSTR contains 5 levels of logic:
Path starting from Comp: P24.IK (from PCI_CLK)
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
P24.I2               Tikri                 2.700R  FRAME_N
                                                   PCI_CORE/PCI_LC/Q1/IFDI/$1I37
CLB_R14C9.G4         net (fanout=28)       7.886R  PCI_CORE/PCI_LC/FRAME-
CLB_R14C9.Y          Tiho                  2.000R  PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/DATA
                                                   I-CNTL/PCI-OFCN/PCI-TRDY/$1I479/PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/EQN-E
                                                   PCI-OFCN/PCI-TRDY/$1I503/PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/DATA_NS_DATA
CLB_R13C3.F4         net (fanout=1)        2.408R  PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/DATA_NS_DATA
CLB_R13C3.X          Tiho                  2.000R  PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/SWAN0
                                                   PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/$1I746
                                                   PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/$3I873
CLB_R13C2.F1         net (fanout=2)        5.130R  PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/SWAN0
CLB_R13C2.Y          Tiho                  2.000R  PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/NS
                                                   I-CNTL/PCI-OFCN/PCI-TRDY/$3I821/PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/SWAN1
                                                   PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/$3I615/$1I8
CLB_R12C5.F4         net (fanout=3)        3.502R  PCI_CORE/PCI_LC/NS_TRDY-
CLB_R12C5.K          Tick                  1.800R  PCI_CORE/PCI_LC/PCI-CNTL/DSTR
                                                   PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/$3I899
                                                   PCI_CORE/PCI_LC/PCI-CNTL/PCI-OFCN/PCI-TRDY/TRDY
-------------------------------------------------
Total (10.500ns logic, 18.926ns route)    29.426ns (to PCI_CLK)
      (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------


All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 27326 paths, 0 nets, and 6233 connections (97.2% coverage)

Design statistics:
   Minimum period:  29.437ns (Maximum frequency:  33.971MHz)


Analysis completed Tue Jun 30 16:02:05 1998
--------------------------------------------------------------------------------