-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: pci_top.ncd Physical constraint file: pci_top.pcf Device,speed: xcs40,-4 (x1_0.14 1.6 PRELIMINARY) Report level: verbose report, limited to 1 item per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "PCLK" PERIOD = 30 nS HIGH 50.000 % ; 26666 items analyzed, 0 timing errors detected. Minimum period is 20.819ns. -------------------------------------------------------------------------------- Slack: 9.181ns path VOY_INST/transfer/n3067 to VOY_INST/transfer/iwf_fifo/n826 relative to 30.000ns delay constraint Path VOY_INST/transfer/n3067 to VOY_INST/transfer/iwf_fifo/n826 contains 10 levels of logic: Path starting from Comp: CLB.K (from PCI_CLK) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB.XQ Tcko 2.100R VOY_INST/transfer/n3067 VOY_INST/transfer/w_overshoot_reg<0>/$1I13 CLB.G1 net (fanout=6) e 0.737R VOY_INST/transfer/w_oops_counter<0> CLB.Y Tilo 1.200R VOY_INST/transfer/n3073 VOY_INST/transfer/U1454 CLB.C3 net (fanout=2) e 0.737R VOY_INST/transfer/n3060 CLB.Y Thh0o 1.900R VOY_INST/transfer/n3042 VOY_INST/transfer/U1453/VOY_INST/transfer/w_reverse CLB.G2 net (fanout=12) e 0.737R VOY_INST/transfer/w_reverse CLB.Y Tilo 1.200R VOY_INST/transfer/iwf_fifo/ram_we VOY_INST/transfer/U1360 CLB.F3 net (fanout=4) e 0.737R VOY_INST/transfer/iwf_move CLB.X Tilo 1.200R VOY_INST/transfer/iwf_fifo/n794 VOY_INST/transfer/iwf_fifo/U465/VOY_INST/transfer/iwf_fifo/n794 CLB.F2 net (fanout=2) e 0.737R VOY_INST/transfer/iwf_fifo/n794 CLB.X Tilo 1.200R VOY_INST/transfer/iwf_fifo/n796 VOY_INST/transfer/iwf_fifo/U550 CLB.C1 net (fanout=13) e 0.737R VOY_INST/transfer/iwf_fifo/n796 CLB.X Thh1o 1.660R VOY_INST/transfer/iwf_fifo/n842 VOY_INST/transfer/iwf_fifo/U511/VOY_INST/transfer/iwf_fifo/n1104 VOY_INST/transfer/iwf_fifo/U424 CLB.F2 net (fanout=1) e 0.737R VOY_INST/transfer/iwf_fifo/n842 CLB.X Tilo 1.200R VOY_INST/transfer/iwf_fifo/n824 VOY_INST/transfer/iwf_fifo/U330 CLB.G2 net (fanout=1) e 0.737R VOY_INST/transfer/iwf_fifo/n824 CLB.Y Tilo 1.200R VOY_INST/transfer/iwf_fifo/n826 VOY_INST/transfer/iwf_fifo/U393 CLB.F1 net (fanout=1) e 0.263R VOY_INST/transfer/iwf_fifo/n826 CLB.K Tick 1.800R VOY_INST/transfer/iwf_fifo/n826 VOY_INST/transfer/iwf_fifo/U389 VOY_INST/transfer/iwf_fifo/almost_full_reg ------------------------------------------------- Total (14.660ns logic, 6.159ns route) 20.819ns (to PCI_CLK) (70.4% logic, 29.6% route) -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 27326 paths, 0 nets, and 6202 connections (97.2% coverage) Design statistics: Minimum period: 20.819ns (Maximum frequency: 48.033MHz) Analysis completed Tue Jun 30 13:43:22 1998 --------------------------------------------------------------------------------