PAR: Xilinx Place And Route M1.5.19. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Jun 30 13:44:06 1998 par -l 4 -d 1 pci_top pci_top_r Constraints file: pci_top.pcf Loading device database for application par from file "pci_top.ncd". "pci_top" is an NCD, version 2.27, device xcs40, package pq240, speed -4 Loading device for application par from file '4020e.nph' in environment /build/xfndry/rtf/x1_5.19. Device speed data version: x1_0.14 1.6 PRELIMINARY. Device utilization summary: Number of External IOBs 175 out of 192 91% Flops: 43 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 541 out of 784 69% Total CLB Flops: 549 out of 1568 35% 4 input LUTs: 856 out of 1568 54% 3 input LUTs: 295 out of 784 37% Number of PRI-CLKs 1 out of 4 25% Number of STARTUPs 1 out of 1 100% Number of TBUFs 320 out of 1680 19% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 5 secs Finished initial Timing Analysis. REAL time: 12 secs Starting initial Placement phase. REAL time: 14 secs Finished initial Placement phase. REAL time: 15 secs Starting Constructive Placer. REAL time: 16 secs Placer score = 3604826 Placer score = 2789753 Placer score = 2206910 Placer score = 1830521 Placer score = 1501524 Placer score = 1372021 Placer score = 1310356 Placer score = 1234802 Placer score = 1149666 Placer score = 1065453 Placer score = 1010380 Placer score = 970263 Placer score = 931749 Placer score = 918840 Placer score = 876371 Placer score = 841642 Placer score = 812304 Placer score = 769612 Placer score = 742100 Placer score = 717427 Placer score = 685681 Placer score = 679667 Placer score = 653387 Placer score = 647280 Placer score = 584717 Placer score = 566857 Placer score = 557379 Placer score = 548515 Placer score = 531086 Placer score = 525112 Placer score = 515900 Placer score = 511213 Placer score = 510489 Placer score = 497560 Placer score = 495655 Placer score = 491126 Placer score = 488859 Placer score = 488690 Placer score = 488428 Placer score = 486829 Placer score = 486154 Placer score = 486005 Placer score = 485222 Placer score = 483968 Placer score = 483733 Placer score = 483425 Placer score = 483301 Finished Constructive Placer. REAL time: 23 mins 23 secs Writing design to file "pci_top_r.ncd". Starting Optimizing Placer. REAL time: 23 mins 24 secs Optimizing ... Swapped 11 comps. Xilinx Placer [1] 481899 REAL time: 24 mins 2 secs Optimizing ... Swapped 4 comps. Xilinx Placer [2] 481899 REAL time: 24 mins 39 secs Finished Optimizing Placer. REAL time: 24 mins 39 secs Writing design to file "pci_top_r.ncd". Total REAL time to Placer completion: 24 mins 41 secs Total CPU time to Placer completion: 23 mins 47 secs 0 connection(s) routed; 4868 unrouted active, 7 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 25 mins 10 secs Starting iterative routing. Routing active signals. End of iteration 1 4839 successful; 29 unrouted active, 7 unrouted PWR/GND; (3736266) REAL time: 26 mins 41 secs End of iteration 2 4856 successful; 12 unrouted active, 7 unrouted PWR/GND; (2239848) REAL time: 29 mins 29 secs End of iteration 3 4858 successful; 10 unrouted active, 7 unrouted PWR/GND; (949790) REAL time: 31 mins 47 secs End of iteration 4 4861 successful; 7 unrouted active, 7 unrouted PWR/GND; (2017815) REAL time: 34 mins 8 secs End of iteration 5 4863 successful; 5 unrouted active, 7 unrouted PWR/GND; (526816) REAL time: 36 mins 7 secs End of iteration 6 4864 successful; 4 unrouted active, 7 unrouted PWR/GND; (297634) REAL time: 38 mins 5 secs End of iteration 7 4865 successful; 3 unrouted active, 7 unrouted PWR/GND; (280608) REAL time: 39 mins 56 secs End of iteration 8 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (353428) REAL time: 41 mins 39 secs End of iteration 9 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (198527) REAL time: 43 mins 56 secs End of iteration 10 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (150068) REAL time: 45 mins 55 secs End of iteration 11 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (144961) REAL time: 48 mins 30 secs End of iteration 12 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (116697) REAL time: 50 mins 13 secs End of iteration 13 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (96293) REAL time: 51 mins 39 secs End of iteration 14 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (89395) REAL time: 53 mins 3 secs End of iteration 15 4866 successful; 2 unrouted active, 7 unrouted PWR/GND; (78503) REAL time: 54 mins 24 secs End of iteration 16 4867 successful; 1 unrouted active, 7 unrouted PWR/GND; (96952) REAL time: 55 mins 37 secs End of iteration 17 4868 successful; 0 unrouted active, 7 unrouted PWR/GND; (99244) REAL time: 56 mins 49 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 18 4875 successful; 0 unrouted; (451072) REAL time: 58 mins 17 secs End of iteration 19 4875 successful; 0 unrouted; (145389) REAL time: 59 mins 35 secs End of iteration 20 4875 successful; 0 unrouted; (102942) REAL time: 1 hrs 51 secs End of iteration 21 4875 successful; 0 unrouted; (96055) REAL time: 1 hrs 2 mins 9 secs End of iteration 22 4875 successful; 0 unrouted; (74731) REAL time: 1 hrs 4 mins 20 secs End of iteration 23 4875 successful; 0 unrouted; (66846) REAL time: 1 hrs 5 mins 28 secs End of iteration 24 4875 successful; 0 unrouted; (52438) REAL time: 1 hrs 6 mins 41 secs End of iteration 25 4875 successful; 0 unrouted; (50259) REAL time: 1 hrs 8 mins 8 secs End of iteration 26 4875 successful; 0 unrouted; (51051) REAL time: 1 hrs 9 mins 17 secs End of iteration 27 4875 successful; 0 unrouted; (42905) REAL time: 1 hrs 10 mins 33 secs End of iteration 28 4875 successful; 0 unrouted; (40093) REAL time: 1 hrs 11 mins 40 secs End of iteration 29 4875 successful; 0 unrouted; (39319) REAL time: 1 hrs 12 mins 54 secs End of iteration 30 4875 successful; 0 unrouted; (26254) REAL time: 1 hrs 14 mins 15 secs End of iteration 31 4875 successful; 0 unrouted; (22739) REAL time: 1 hrs 15 mins 29 secs End of iteration 32 4875 successful; 0 unrouted; (22739) REAL time: 1 hrs 16 mins 47 secs End of iteration 33 4875 successful; 0 unrouted; (22478) REAL time: 1 hrs 19 mins 19 secs End of iteration 34 4875 successful; 0 unrouted; (14328) REAL time: 1 hrs 20 mins 57 secs End of iteration 35 4875 successful; 0 unrouted; (13769) REAL time: 1 hrs 22 mins 47 secs End of iteration 36 4875 successful; 0 unrouted; (13152) REAL time: 1 hrs 24 mins 36 secs End of iteration 37 4875 successful; 0 unrouted; (8355) REAL time: 1 hrs 26 mins 7 secs Writing design to file "pci_top_r.ncd". End of iteration 38 4875 successful; 0 unrouted; (8847) REAL time: 1 hrs 27 mins 26 secs End of iteration 39 4875 successful; 0 unrouted; (8847) REAL time: 1 hrs 28 mins 34 secs End of iteration 40 4875 successful; 0 unrouted; (7301) REAL time: 1 hrs 29 mins 32 secs End of iteration 41 4875 successful; 0 unrouted; (7301) REAL time: 1 hrs 30 mins 48 secs End of iteration 42 4875 successful; 0 unrouted; (2185) REAL time: 1 hrs 31 mins 59 secs End of iteration 43 4875 successful; 0 unrouted; (1982) REAL time: 1 hrs 33 mins 32 secs End of iteration 44 4875 successful; 0 unrouted; (1926) REAL time: 1 hrs 36 mins 35 secs End of iteration 45 4875 successful; 0 unrouted; (1926) REAL time: 1 hrs 38 mins 9 secs End of iteration 46 4875 successful; 0 unrouted; (1926) REAL time: 1 hrs 39 mins 26 secs End of iteration 47 4875 successful; 0 unrouted; (1926) REAL time: 1 hrs 40 mins 43 secs End of iteration 48 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 42 mins 13 secs End of iteration 49 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 44 mins 2 secs End of iteration 50 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 46 mins 58 secs End of iteration 51 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 48 mins 37 secs End of iteration 52 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 49 mins 55 secs End of iteration 53 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 51 mins 11 secs Ending automatic router iterations. Writing design to file "pci_top_r.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 4875 successful; 0 unrouted; (1870) REAL time: 1 hrs 53 mins 18 secs Writing design to file "pci_top_r.ncd". Starting delay cleanup Improving timing. End of delay cleanup iteration 1 4875 successful; 0 unrouted; (1340) REAL time: 1 hrs 55 mins 42 secs Writing design to file "pci_top_r.ncd". Total REAL time: 1 hrs 55 mins 46 secs Total CPU time: 1 hrs 40 mins 57 secs End of route. 4875 routed (100.00%); 0 unrouted. No errors found. The signal "PCI_CORE/PCI_LC/BAR2/NLMEM" has no loads so was not routed. The signal "PCI_CORE/PCI_LC/BAR2/BHIT" has no loads so was not routed. The signal "PCI_CORE/PCI_LC/BAR1/NLMEM" has no loads so was not routed. The signal "PCI_CORE/PCI_LC/BAR1/BHIT" has no loads so was not routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 1 hrs 55 mins 50 secs Total CPU time to Router completion: 1 hrs 40 mins 59 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 1660 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.299 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.165 ns The Maximum Pin Delay is: 18.039 ns The Average Connection Delay on the 10 Worst Nets is: 15.180 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 4377 210 0 0 0 0 Timing Score: 1340 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * NET "PCLK" PERIOD = 30 nS HIGH 50.000 | 30.000ns | 31.340ns | 7 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "pci_top_r.ncd". All signals are completely routed. Total REAL time to PAR completion: 1 hrs 56 mins 6 secs Total CPU time to PAR completion: 1 hrs 41 mins 9 secs PAR done.