-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: pci_top_r.ncd Physical constraint file: pci_top.pcf Device,speed: xcs40,-4 (x1_0.14 1.6 PRELIMINARY) Report level: verbose report, limited to 1 item per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "PCLK" PERIOD = 30 nS HIGH 50.000 % ; 26666 items analyzed, 1 timing error detected. Minimum period is 31.340ns. -------------------------------------------------------------------------------- Slack: -1.340ns path VOY_INST/len<4> to VOY_INST/registers/n1360 relative to 30.000ns delay constraint Path VOY_INST/len<4> to VOY_INST/registers/n1360 contains 7 levels of logic: Path starting from Comp: CLB_R21C18.K (from PCI_CLK) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R21C18.XQ Tcko 2.100R VOY_INST/len<4> VOY_INST/registers/xfer_leni/len_bits_reg<3> CLB_R7C17.G1 net (fanout=5) 5.893R VOY_INST/len<5> CLB_R7C17.Y Tilo 1.200R VOY_INST/registers/n1359 VOY_INST/registers/U716/VOY_INST/registers/n1365 CLB_R21C17.F4 net (fanout=1) 8.455R VOY_INST/registers/n1365 CLB_R21C17.X Tilo 1.200R VOY_INST/registers/n1402 VOY_INST/registers/U797 TBUF_R21C17.1.I net (fanout=1) 0.017R VOY_INST/registers/n1402 TBUF_R21C17.1.O Tio 2.659R VOY_INST/registers/U567 VOY_INST/registers/U567 CLB_R21C20.F4 net (fanout=5) 1.785R ADIO<21> CLB_R21C20.X Tilo 1.200R VOY_INST/registers/xfer_padri/input_mh<5> VOY_INST/registers/xfer_padri/U237 CLB_R18C20.G3 net (fanout=1) 1.391R VOY_INST/registers/xfer_padri/input_mh<5> CLB_R18C20.Y Tilo 1.200R VOY_INST/registers/xfer_padri/count2/ORL4_OUT VOY_INST/registers/xfer_padri/count2/ORL5 CLB_R11C20.C2 net (fanout=1) 2.940R VOY_INST/registers/xfer_padri/count2/ORL5_OUT CLB_R11C20.K Tdick 1.300R VOY_INST/registers/n1360 VOY_INST/registers/xfer_padri/count2/FLOP5 ------------------------------------------------- Total (10.859ns logic, 20.481ns route) 31.340ns (to PCI_CLK) (34.6% logic, 65.4% route) -------------------------------------------------------------------------------- 1 constraint not met. Timing summary: --------------- Timing errors: 1 Score: 1340 Constraints cover 27326 paths, 0 nets, and 6202 connections (97.2% coverage) Design statistics: Minimum period: 31.340ns (Maximum frequency: 31.908MHz) Analysis completed Tue Jun 30 16:02:21 1998 --------------------------------------------------------------------------------