PAR: Xilinx Place And Route M1.4.8. Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Mon Sep 8 09:34:46 1997 par -gm exact -gf ../top_r.ncd top_fsmstate.ncd top_fsmstate_pge_only.ncd top_66.pcf Constraints file: top_66.pcf Placer effort level (-pl): 4 Placer cost table entry (-t): 1 Router effort level (-rl): 4 Loading device database for application par from file "top_fsmstate.ncd". "top_fsmstate" is an NCD, version 2.27, device xc4028xl, package hq240, speed -1 Loading device for application par from file '4028ex.nph' in environment /build/xfndry/rtf/x1_4.8. Device speed data version: x1_0.09 3.7f PRELIMINARY. Loading device database for application par from file "../top_r.ncd". "top" is an NCD, version 2.27, device xc4028xl, package hq240, speed -1 Running DRC on the Guide design. Finished running DRC on the Guide design. Running DRC on the Target design. Finished running DRC on the Target design. Starting guide file placement. Placed 938 out of 945 comps in the new design. Checking signals and doing guided routing. The signal "n266" has different connectivity in the current design than it has in the guide design. The component "n576" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_config_regs/n1312" has different connectivity in the current design than it has in the guide design. The signal "n306" has different connectivity in the current design than it has in the guide design. The signal "n307" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/addr_phase_par" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/serr_n3203" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<16>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<14>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<12>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<10>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<8>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<6>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<4>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<2>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<24>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<22>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<20>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<18>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/counter_reg12969<0>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/sub_2178/u28/S0_1/CY4_0" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<16>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<14>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<12>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<10>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<8>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<6>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<4>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<2>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<26>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<24>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<22>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<20>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<18>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/address_reg12959<0>" has different connectivity in the current design than it has in the guide design. The component "dwart_a/add_2175/u28/S0_1/CY4_0" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_config_regs/n1449" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r287/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_xpci_mux/n787" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n343" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n337" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r279/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r279/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r279/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r259/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r259/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r259/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r259/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r219/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r219/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r219/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r219/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r283/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r283/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r283/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r283/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n324" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r235/u12/S0/SUB/CY4_5" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r235/u12/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r235/u12/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r235/u12/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r235/u12/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r227/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r227/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r227/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r227/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r255/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r255/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r255/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r255/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_6" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_5" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r215/u12/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r247/u8/S0/SUB/CY4_4" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r247/u8/S0/SUB/CY4_3" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r247/u8/S0/SUB/CY4_2" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_decode/r247/u8/S0/SUB/CY4_1" has different connectivity in the current design than it has in the guide design. The signal "_pc_trdy" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n1091<0>", which contains a route-through, cannnot be routed as directed by the guide design, because the route-through is no longer available. The component "dwart_a/n6943" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/mem_rd_reg" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<23>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n11911" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_xpci_mux/n793" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_config_regs/rd_addr_diag_reg<28>" has different connectivity in the current design than it has in the guide design. The signal "dpci/local_io_rd" has different connectivity in the current design than it has in the guide design. The signal "dpci/cmd_reg<3>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n344" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<11>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<17>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<11>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n468" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n485" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n484" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_ipci_mux/n516" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11772" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<21>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<9>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<12>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<13>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/new_state<21>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/n11808" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<1>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<4>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<7>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<3>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<6>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11683" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<5>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<5>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11681" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11817" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<18>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<18>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/be_en_2_ipci3284" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11736" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<26>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<20>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<21>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11718" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<20>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<21>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11687" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<3>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11800" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state3149<18>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state3149<5>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<15>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state3149<18>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11680" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<23>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n11679" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n856<0>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n11982" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/par_in_reg" has different connectivity in the current design than it has in the guide design. The component "dpci/cap_data_wr<0>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11749" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11660" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11677" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11789" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state<14>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11793" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n3150<26>/2.0" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<5>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n3150<26>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n3150<26>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n3123/2.1" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11832" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11673" has different connectivity in the current design than it has in the guide design. The component "dpci/cap_data_wr<28>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11709" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<1>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n11727" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11690" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11778/2.0" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n12224" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11846" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11733" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<8>" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<10>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11853" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11750" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<6>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11776" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<6>" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<20>" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<22>" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<26>" has different connectivity in the current design than it has in the guide design. The component "dpci/addr_reg<28>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/new_state3149<5>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/new_state<1>" in the current design does not match any components in the guide file. The component "dpci/cap_data_rd<28>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11672" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<9>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<23>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/new_state3149<13>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<9>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11675" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<4>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<4>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11748" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<18>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/perr_en_early3311" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12431" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n12201/2.0" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/serr_n3203" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/n11694" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11694" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11727" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<14>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11725" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12419" has different connectivity in the current design than it has in the guide design. The component "dpci/mem_rd" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state3149<18>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/new_state<11>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/new_state<17>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/n11755" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11659" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<17>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<14>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11744" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<1>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12274" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<1>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11707" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11667" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11663" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<20>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11670" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11674" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11706" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12299" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11692" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<5>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<7>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n3231" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<9>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11669" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<14>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<11>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/new_state<20>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/n12462" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12360" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<15>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12458" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12363" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12378" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<5>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12405/2.0" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11742" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<4>" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<3>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11686" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<1>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/pc_irdy_n" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n11719" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<17>" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/n12437" has different connectivity in the current design than it has in the guide design. The component "dpci/pci_fsm/new_state<7>" in the current design does not match any components in the guide file. The component "dpci/pci_fsm/n11734" has different connectivity in the current design than it has in the guide design. The signal "dpci/pci_fsm/state<9>" has different connectivity in the current design than it has in the guide design. Checking guided macros. Checking and setting the sanity of the guided routes. Done. Guide file processing done. Device utilization summary: Number of External IOBs 99 out of 193 51% Flops: 2 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 761 out of 1024 74% Total Latches: 0 out of 2048 1% Total CLB Flops: 529 out of 2048 25% 4 input LUTs: 1198 out of 2048 58% 3 input LUTs: 344 out of 1024 33% Number of BUFGLSs 1 out of 8 12% Number of TBUFs 84 out of 2176 3% Starting initial Timing Analysis. REAL time: 2 mins 48 secs Finished initial Timing Analysis. REAL time: 8 mins 13 secs Starting initial Placement phase. REAL time: 8 mins 29 secs Finished initial Placement phase. REAL time: 8 mins 33 secs Dumping design to file "top_fsmstate_pge_only.ncd". Starting Optimizing Placer. REAL time: 8 mins 39 secs Optimizing Swapped 36 comps. Xilinx Placer [1] 1205386 REAL time: 8 mins 50 secs Optimizing Swapped 18 comps. Xilinx Placer [2] 1097874 REAL time: 8 mins 57 secs Finished Optimizing Placer. REAL time: 8 mins 57 secs Dumping design to file "top_fsmstate_pge_only.ncd". Total REAL time to Placer completion: 9 mins 8 secs Total CPU time to Placer completion: 8 mins 31 secs 4973 connection(s) routed; 782 unrouted active, 161 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 1 hrs 15 mins 47 secs Starting iterative routing. End of iteration 1 5755 successful; 0 unrouted active, 161 unrouted PWR/GND; (1487798) REAL time: 2 hrs 20 mins 31 secs End of iteration 2 5755 successful; 0 unrouted active, 161 unrouted PWR/GND; (1436169) REAL time: 3 hrs 24 mins 23 secs Dumping design to file "top_fsmstate_pge_only.ncd". Power and ground nets completely routed. End of iteration 3 5916 successful; 0 unrouted; (1433633) REAL time: 4 hrs 31 mins 45 secs Dumping design to file "top_fsmstate_pge_only.ncd". Total CPU time: 4 hrs 19 mins 52 secs Total REAL time: 4 hrs 32 mins 56 secs Completely routed. End of route. 5916 routed (100.00%); 0 unrouted. No errors found. Total REAL time to Router completion: 4 hrs 33 mins 20 secs Total CPU time to Router completion: 4 hrs 20 mins 15 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 1038922 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 5.896 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.332 ns The Maximum Pin Delay is: 41.599 ns The Average Connection Delay on the 10 Worst Nets is: 33.015 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 4817 900 101 50 7 0 Timing Score: 1433633 WARNING:baspw:101 - Timing constraints have not been met. Dumping design to file "top_fsmstate_pge_only.ncd". All signals are completely routed. Total REAL time to PAR completion: 4 hrs 24 mins 4 secs Total CPU time to PAR completion: 4 hrs 24 mins 4 secs PAR done after being halted.