PAR: Xilinx Place And Route M1.4.8. Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Thu Sep 4 14:41:33 1997 par -pl 4 -rl 2 top top_r Constraints file: top.pcf Placer effort level (-pl): 4 Placer cost table entry (-t): 1 Router effort level (-rl): 2 Loading device database for application par from file "top.ncd". "top" is an NCD, version 2.27, device xc4028xl, package hq240, speed -1 Loading device for application par from file '4028ex.nph' in environment /build/xfndry/rtf/x1_4.8. Device speed data version: x1_0.08 3.7f PRELIMINARY. Device utilization summary: Number of External IOBs 99 out of 193 51% Flops: 2 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 761 out of 1024 74% Total Latches: 0 out of 2048 1% Total CLB Flops: 529 out of 2048 25% 4 input LUTs: 1198 out of 2048 58% 3 input LUTs: 344 out of 1024 33% Number of BUFGLSs 1 out of 8 12% Number of TBUFs 84 out of 2176 3% Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 1 mins 4 secs Starting initial Placement phase. REAL time: 1 mins 7 secs Finished initial Placement phase. REAL time: 1 mins 8 secs Starting Constructive Placer. REAL time: 1 mins 10 secs Placer score = 4307866 Placer score = 3678489 Placer score = 3169591 Placer score = 2686684 Placer score = 2267432 Placer score = 2075570 Placer score = 1595481 Placer score = 1381980 Placer score = 1126130 Placer score = 995637 Placer score = 866370 Placer score = 770326 Placer score = 693425 Placer score = 633667 Placer score = 603951 Placer score = 519173 Placer score = 507474 Placer score = 497209 Placer score = 485863 Placer score = 476074 Placer score = 469163 Placer score = 464281 Placer score = 459646 Placer score = 456637 Placer score = 453737 Placer score = 452340 Placer score = 450202 Placer score = 448761 Placer score = 447678 Placer score = 446397 Placer score = 444752 Placer score = 423692 Placer score = 423542 Finished Constructive Placer. REAL time: 48 mins 7 secs Dumping design to file "top_r.ncd". Starting Optimizing Placer. REAL time: 48 mins 8 secs Optimizing ........... Swapped 124 comps. Xilinx Placer [1] 414419 REAL time: 50 mins 6 secs Optimizing .......... Swapped 20 comps. Xilinx Placer [2] 413540 REAL time: 51 mins 56 secs Optimizing .......... Swapped 3 comps. Xilinx Placer [3] 413480 REAL time: 53 mins 43 secs Finished Optimizing Placer. REAL time: 53 mins 43 secs Dumping design to file "top_r.ncd". Total REAL time to Placer completion: 53 mins 46 secs Total CPU time to Placer completion: 53 mins 36 secs 0 connection(s) routed; 5755 unrouted active, 161 unrouted PWR/GND. Starting router resource preassignment Completed router resource preassignment. REAL time: 1 hrs 5 mins 13 secs Starting iterative routing. End of iteration 1 5755 successful; 0 unrouted active, 161 unrouted PWR/GND; (359599604) REAL time: 1 hrs 22 mins 29 secs End of iteration 2 5755 successful; 0 unrouted active, 161 unrouted PWR/GND; (0) REAL time: 1 hrs 37 mins 50 secs Constraints are met. Power and ground nets completely routed. Total CPU time: 1 hrs 34 mins 27 secs Total REAL time: 1 hrs 38 mins 5 secs Completely routed. End of route. 5916 routed (100.00%); 0 unrouted. No errors found. Total REAL time to Router completion: 1 hrs 38 mins 10 secs Total CPU time to Router completion: 1 hrs 34 mins 31 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 1311 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 6.138 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.332 ns The Maximum Pin Delay is: 43.509 ns The Average Connection Delay on the 10 Worst Nets is: 34.901 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 4758 920 121 58 18 0 Timing Score: 0 Dumping design to file "top_r.ncd". All signals are completely routed. Total REAL time to PAR completion: 1 hrs 34 mins 53 secs Total CPU time to PAR completion: 1 hrs 34 mins 53 secs PAR done.