-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.4.8 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Design file: top_r.ncd Physical constraint file: top.pcf Device,speed: xc4028xl,-1 (x1_0.08 3.7f PRELIMINARY) Report level: verbose report, limited to 10 items per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS01 = PERIOD ALLCLOCKNETS 80 ; 351263 items analyzed, 0 timing errors detected. Minimum period is 72.931ns. -------------------------------------------------------------------------------- Slack: 7.069ns path dwart_a/dma_state7041<26> to dwart_a/n24749 relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/n24749 contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R13C12.G4 net (fanout=5) 3.884R dwart_a/n24419 CLB_R13C12.Y Tilo 1.300R dwart_a/n24360 dwart_a/n24420 CLB_R7C12.G1 net (fanout=8) 10.531R dwart_a/n24420 CLB_R7C12.Y Tilo 1.300R dwart_a/n6745 dwart_a/n6754 CLB_R6C13.F2 net (fanout=2) 1.780R dwart_a/n6754 CLB_R6C13.X Tilo 1.300R dwart_a/n6736 dwart_a/n6736 CLB_R6C15.C2 net (fanout=1) 1.434R dwart_a/n6736 CLB_R6C15.K Tecck 0.920R dwart_a/n24749 dwart_a/receive_error_0 ------------------------------------------------- Total (16.138ns logic, 56.793ns route) 72.931ns (to n266) (22.1% logic, 77.9% route) -------------------------------------------------------------------------------- Slack: 7.516ns path dwart_a/dma_state7041<26> to dwart_a/n24417 relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/n24417 contains 13 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R19C10.F4 net (fanout=2) 2.043R dwart_a/n24448 CLB_R19C10.X Tiho 2.140R dwart_a/n6943 dwart_a/n6943/2.0 dwart_a/n6943 CLB_R16C13.C4 net (fanout=2) 2.214R dwart_a/n6943 CLB_R16C13.Y Thh1o 1.850R dwart_a/n6826 dwart_a/n6853 CLB_R13C13.C3 net (fanout=1) 1.322R dwart_a/n6853 CLB_R13C13.K Tecck 0.920R dwart_a/n24417 dwart_a/n27168 ------------------------------------------------- Total (19.668ns logic, 52.816ns route) 72.484ns (to n266) (27.1% logic, 72.9% route) -------------------------------------------------------------------------------- Slack: 8.154ns path dwart_a/dma_state7041<26> to dpci/pci_fsm/cap_state<0> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dpci/pci_fsm/cap_state<0> contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R21C10.C2 net (fanout=45) 6.083R dwart_a/n7976<0> CLB_R21C10.K Tecck 0.920R dpci/pci_fsm/cap_state<0> dwart_a/xmit_reg<44> ------------------------------------------------- Total (17.818ns logic, 54.028ns route) 71.846ns (to n266) (24.8% logic, 75.2% route) -------------------------------------------------------------------------------- Slack: 8.459ns path dwart_a/dma_state7041<26> to dwart_a/n27097 relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/n27097 contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R18C19.C4 net (fanout=45) 5.778R dwart_a/n7976<0> CLB_R18C19.K Tecck 0.920R dwart_a/n27097 dwart_a/xmit_reg<12> ------------------------------------------------- Total (17.818ns logic, 53.723ns route) 71.541ns (to n266) (24.9% logic, 75.1% route) -------------------------------------------------------------------------------- Slack: 8.556ns path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<13> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<13> contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R22C18.C2 net (fanout=45) 5.681R dwart_a/n7976<0> CLB_R22C18.K Tecck 0.920R dwart_a/xmit_reg<13> dwart_a/xmit_reg<13> ------------------------------------------------- Total (17.818ns logic, 53.626ns route) 71.444ns (to n266) (24.9% logic, 75.1% route) -------------------------------------------------------------------------------- Slack: 8.565ns path dwart_a/dma_state7041<26> to dwart_a/address_reg<22> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/address_reg<22> contains 11 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R13C13.F3 net (fanout=7) 5.458R dwart_a/n24355 CLB_R13C13.X Tilo 1.300R dwart_a/n24417 dwart_a/n24417 CLB_R13C11.C2 net (fanout=12) 2.636R dwart_a/n24417 CLB_R13C11.X Thh0o 1.990R dwart_a/n24375 dwart_a/n24375 CLB_R11C13.F3 net (fanout=5) 2.707R dwart_a/n24375 CLB_R11C13.X Tilo 1.300R dwart_a/n24451 dwart_a/n24451 CLB_R9C14.F3 net (fanout=2) 3.364R dwart_a/n24451 CLB_R9C14.X Tilo 1.300R dwart_a/n7982<0> dwart_a/n7982<0> CLB_R5C24.C4 net (fanout=28) 9.441R dwart_a/n7982<0> CLB_R5C24.K Tecck 0.920R dwart_a/address_reg<22> dwart_a/address_reg<23> ------------------------------------------------- Total (14.978ns logic, 56.457ns route) 71.435ns (to n266) (21.0% logic, 79.0% route) -------------------------------------------------------------------------------- Slack: 8.565ns path dwart_a/dma_state7041<26> to dwart_a/address_reg<22> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/address_reg<22> contains 11 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R13C13.F3 net (fanout=7) 5.458R dwart_a/n24355 CLB_R13C13.X Tilo 1.300R dwart_a/n24417 dwart_a/n24417 CLB_R13C11.C2 net (fanout=12) 2.636R dwart_a/n24417 CLB_R13C11.X Thh0o 1.990R dwart_a/n24375 dwart_a/n24375 CLB_R11C13.F3 net (fanout=5) 2.707R dwart_a/n24375 CLB_R11C13.X Tilo 1.300R dwart_a/n24451 dwart_a/n24451 CLB_R9C14.F3 net (fanout=2) 3.364R dwart_a/n24451 CLB_R9C14.X Tilo 1.300R dwart_a/n7982<0> dwart_a/n7982<0> CLB_R5C24.C4 net (fanout=28) 9.441R dwart_a/n7982<0> CLB_R5C24.K Tecck 0.920R dwart_a/address_reg<22> dwart_a/address_reg<22> ------------------------------------------------- Total (14.978ns logic, 56.457ns route) 71.435ns (to n266) (21.0% logic, 79.0% route) -------------------------------------------------------------------------------- Slack: 8.608ns path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<23> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<23> contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R19C18.C1 net (fanout=45) 5.629R dwart_a/n7976<0> CLB_R19C18.K Tecck 0.920R dwart_a/xmit_reg<23> dwart_a/xmit_reg<23> ------------------------------------------------- Total (17.818ns logic, 53.574ns route) 71.392ns (to n266) (25.0% logic, 75.0% route) -------------------------------------------------------------------------------- Slack: 8.681ns path dwart_a/dma_state7041<26> to dwart_a/n24521 relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/n24521 contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R16C16.C2 net (fanout=45) 5.556R dwart_a/n7976<0> CLB_R16C16.K Tecck 0.920R dwart_a/n24521 dwart_a/xmit_reg<27> ------------------------------------------------- Total (17.818ns logic, 53.501ns route) 71.319ns (to n266) (25.0% logic, 75.0% route) -------------------------------------------------------------------------------- Slack: 8.781ns path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<34> relative to 80.000ns delay constraint Path dwart_a/dma_state7041<26> to dwart_a/xmit_reg<34> contains 12 levels of logic: Path starting from Comp: CLB_R9C17.K (from n266) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C17.XQ Tcko 1.579R dwart_a/dma_state7041<26> dwart_a/addr_reg_en CLB_R14C19.G1 net (fanout=30) ~ 18.635R dwart_a/addr_reg_en CLB_R14C19.Y Tilo 1.300R dwart_a/n24463 dwart_a/n24542 CLB_R16C21.G4 net (fanout=2) 2.699R dwart_a/n24542 CLB_R16C21.Y Tilo 1.300R dwart_a/n24865 dwart_a/n24867 TBUF_R16C21.1.I net (fanout=1) 0.101R dwart_a/n24867 TBUF_R16C21.1.O Tio 0.549R dwart_a/U9938 CLB_R15C16.G3 net (fanout=4) 7.763R pc_ad<7> CLB_R15C16.Y Tiho 2.140R dwart_a/n24352 dwart_a/n26699 dwart_a/n24352 CLB_R11C16.F1 net (fanout=4) 3.653R dwart_a/n24352 CLB_R11C16.X Tilo 1.300R dwart_a/n24355 dwart_a/n24355 CLB_R12C14.G1 net (fanout=7) 3.121R dwart_a/n24355 CLB_R12C14.Y Tilo 1.300R dwart_a/n6871 dwart_a/n24358 CLB_R14C15.C4 net (fanout=5) 3.192R dwart_a/n24358 CLB_R14C15.Y Thh1o 1.850R dwart_a/n24529 dwart_a/n24419 CLB_R12C12.F4 net (fanout=5) 3.642R dwart_a/n24419 CLB_R12C12.X Tilo 1.300R dwart_a/n24422 dwart_a/n24422 CLB_R18C13.G2 net (fanout=5) 4.431R dwart_a/n24422 CLB_R18C13.Y Tiho 2.140R dwart_a/n24783 dwart_a/n26268/2.0 dwart_a/n24448 CLB_R18C14.F1 net (fanout=2) 0.708R dwart_a/n24448 CLB_R18C14.Y Tiho 2.140R dwart_a/n6934 dwart_a/n6934 dwart_a/n7976<0> CLB_R15C14.C2 net (fanout=45) 5.456R dwart_a/n7976<0> CLB_R15C14.K Tecck 0.920R dwart_a/xmit_reg<34> dwart_a/xmit_reg<34> ------------------------------------------------- Total (17.818ns logic, 53.401ns route) 71.219ns (to n266) (25.0% logic, 75.0% route) -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 351263 paths, 0 nets, and 5425 connections (93.2% coverage) Design statistics: Minimum period: 72.931ns (Maximum frequency: 13.712MHz) Analysis completed Thu Sep 4 16:45:48 1997 --------------------------------------------------------------------------------