ngdbuild -p xc4002xl-09-pc84 -uc d:\xilinx\active\projects\map_lab\map_lab.ucf -dd .. d:\xilinx\active\projects\map_lab\map_lab.edn map_lab.ngd ngdbuild: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4002xl-09-pc84 -uc d:\xilinx\active\projects\map_lab\map_lab.ucf -dd .. d:\xilinx\active\projects\map_lab\map_lab.edn map_lab.ngd Launcher: Executing edif2ngd "d:\xilinx\active\projects\map_lab\map_lab.edn" "H:\eng_labs\map_lab\xproj\ver1\map_lab.ngo" edif2ngd: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Writing the design to "H:/eng_labs/map_lab/xproj/ver1/map_lab.ngo"... Reading NGO file "H:/eng_labs/map_lab/xproj/ver1/map_lab.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "d:/xilinx/active/projects/map_lab/map_lab.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGD file "map_lab.ngd" ... Writing NGDBUILD log file "map_lab.bld"... NGDBUILD done. ================================================== map -p xc4002xl-09-pc84 -o map.ncd -pr b map_lab.ngd map_lab.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "map_lab.ngd"... Using target part "4002xlpc84-09". MAP xc4000xl directives: Partname = "xc4002xl-09-pc84". Covermode = "area". Pack registers into both input and output IOBs. Pack CLBs to 100%. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 1 Number of CLBs: 6 out of 64 9% CLB Flip Flops: 8 CLB Latches: 0 4 input LUTs: 11 (1 used as route-throughs) 3 input LUTs: 1 Number of bonded IOBs: 23 out of 61 37% IOB Flops: 1 IOB Latches: 0 Number of clock IOB pads: 1 out of 12 8% Number of BUFGLSs: 1 out of 8 12% Number of RPM macros: 1 Total equivalent gate count for design: 174 Additional JTAG gate count for IOBs: 1104 Writing design file "map.ncd"... Removed Logic Summary: 2 block(s) optimized away Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 2 -d 0 map.ncd map_lab.ncd map_lab.pcf PAR: Xilinx Place And Route M1.5.19. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: map_lab.pcf Loading device database for application par from file "map.ncd". "map_lab" is an NCD, version 2.27, device xc4002xl, package pc84, speed -09 Loading device for application par from file '4002xl.nph' in environment d:/xilinx. Device speed data version: x1_0.37 1.22 PRELIMINARY. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 22 out of 61 36% Flops: 1 Latches: 0 Number of Global Buffer IOBs 1 out of 8 12% Flops: 0 Latches: 0 Number of CLBs 6 out of 64 9% Total Latches: 0 out of 128 0% Total CLB Flops: 8 out of 128 6% 4 input LUTs: 11 out of 128 8% 3 input LUTs: 1 out of 64 1% Number of BUFGLSs 1 out of 8 12% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Starting initial Placement phase. REAL time: 4 secs Finished initial Placement phase. REAL time: 4 secs Starting Constructive Placer. REAL time: 4 secs Placer score = 4920 Placer score = 4170 Placer score = 3330 Finished Constructive Placer. REAL time: 4 secs Writing design to file "map_lab.ncd". Starting Optimizing Placer. REAL time: 4 secs Optimizing Swapped 46 comps. Xilinx Placer [1] 2220 REAL time: 4 secs Finished Optimizing Placer. REAL time: 4 secs Writing design to file "map_lab.ncd". Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 3 secs 0 connection(s) routed; 56 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 4 secs Starting iterative routing. Routing active signals. End of iteration 1 56 successful; 0 unrouted; (0) REAL time: 4 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "map_lab.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 56 successful; 0 unrouted; (0) REAL time: 5 secs Writing design to file "map_lab.ncd". Total REAL time: 5 secs Total CPU time: 3 secs End of route. 56 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 5 secs Total CPU time to Router completion: 3 secs Generating PAR statistics. Writing design to file "map_lab.ncd". All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 4 secs PAR done. ================================================== trce map_lab.ncd map_lab.pcf -e 3 -o map_lab.twr Loading device database for application trce from file "map_lab.ncd". "map_lab" is an NCD, version 2.27, device xc4002xl, package pc84, speed -09 Loading device for application trce from file '4002xl.nph' in environment d:/xilinx. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: map_lab.ncd Physical constraint file: map_lab.pcf Device,speed: xc4002xl,-09 (x1_0.37 1.22 PRELIMINARY) Report level: error report, limited to 3 items per constraint -------------------------------------------------------------------------------- WARNING:bastw:170 - No timing constraints found, doing default enumeration. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 126 paths, 30 nets, and 56 connections (100.0% coverage) Design statistics: Minimum period: 8.778ns (Maximum frequency: 113.921MHz) Maximum combinational path delay: 13.685ns Maximum net delay: 4.277ns Analysis completed Tue Oct 06 16:07:10 1998 -------------------------------------------------------------------------------- Total time: 4 secs ================================================== bitgen map_lab.ncd -l -w -f bitgen.ut Loading device database for application Bitgen from file "map_lab.ncd". "map_lab" is an NCD, version 2.27, device xc4002xl, package pc84, speed -09 Loading device for application Bitgen from file '4002xl.nph' in environment d:/xilinx. Opened constraints file map_lab.pcf. BITGEN: Xilinx Bitstream Generator M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 16:07:14 1998 Running DRC. DRC detected 0 errors and 0 warnings. Saving ll file in "map_lab.ll". Creating bit map... Saving bit stream in "map_lab.bit". ================================================== xcpy map_lab.bit d:\xilinx\active\projects\map_lab\map_lab.bit ================================================== xcpy map_lab.ll d:\xilinx\active\projects\map_lab\map_lab.ll