Xilinx Mapping Report File for Design "map_lab"
          Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Design Information
------------------
Command Line   : map -p xc4002xl-09-pc84 -o map.ncd -pr b map_lab.ngd
map_lab.pcf 
Target Device  : x4002xl
Target Package : pc84
Target Speed   : -09
Mapper Version : xc4000xl -- M1.5.19
Mapped Date    : Tue Oct 06 16:06:55 1998

Design Summary
--------------
   Number of errors:        0
   Number of warnings:      1
   Number of CLBs:              6 out of    64    9%
      CLB Flip Flops:       8
      CLB Latches:          0
      4 input LUTs:        11 (1 used as route-throughs)
      3 input LUTs:         1
   Number of bonded IOBs:      23 out of    61   37%
      IOB Flops:            1
      IOB Latches:          0
   Number of clock IOB pads:    1 out of    12    8%
   Number of BUFGLSs:           1 out of     8   12%
   Number of RPM macros:        1
Total equivalent gate count for design: 174
Additional JTAG gate count for IOBs:    1104

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Design Attributes
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - Added Logic
Section 7 - Expanded Logic
Section 8 - Signal Cross-Reference
Section 9 - Symbol Cross-Reference
Section 10 - IOB Properties
Section 11 - RPMs
Section 12 - Guide Report

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:baste:24 - All of the external outputs in this design are using
   slew-rate-limited output drivers.  The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the original
   design.  Please see your vendor interface documentation for specific
   information on how to do this within your design-entry tool.
   Note: You should be careful not to designate too many outputs which switch
   together as fast, because this can cause excessive ground bounce.  For more
   information on this subject, please refer to the IOB switching characteristic
   guidelines for the device you are using in the Programmable Logic Data Book.

Section 3 - Design Attributes
-----------------------------

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
VCC 		$I5/$1I40
GND 		$I5/$1I43

Section 6 - Added Logic
-----------------------

Section 7 - Expanded Logic
--------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 8 - Signal Cross-Reference
----------------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 9 - Symbol Cross-Reference
----------------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 10 - IOB Properties
---------------------------
$Net00007_ (IOB) : SLEW=SLOW
$Net00009_ (IOB) : SLEW=SLOW
COUNT<0> (IOB) : SLEW=SLOW
COUNT<1> (IOB) : SLEW=SLOW
COUNT<2> (IOB) : SLEW=SLOW
COUNT<3> (IOB) : SLEW=SLOW
COUNT<4> (IOB) : SLEW=SLOW
COUNT<5> (IOB) : SLEW=SLOW
COUNT<6> (IOB) : SLEW=SLOW
COUNT<7> (IOB) : SLEW=SLOW
LOAD_A (IOB) : INFF

Section 11 - RPMs
-----------------
$I7/hset                                 - 5 comps

Section 12 - Guide Report
-------------------------
Guide not run on this design.