PAR: Xilinx Place And Route M1.5.19.
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Tue Oct 06 16:06:59 1998

par -w -ol 2 -d 0 map.ncd map_lab.ncd map_lab.pcf


Constraints file: map_lab.pcf

Loading device database for application par from file "map.ncd".
   "map_lab" is an NCD, version 2.27, device xc4002xl, package pc84, speed -09
Loading device for application par from file '4002xl.nph' in environment
d:/xilinx.
Device speed data version:  x1_0.37 1.22 PRELIMINARY.


Device utilization summary:

   Number of External IOBs            22 out of 61     36%
      Flops:                           1
      Latches:                         0
   Number of Global Buffer IOBs        1 out of 8      12%
      Flops:                           0
      Latches:                         0

   Number of CLBs                      6 out of 64      9%
      Total Latches:                   0 out of 128     0%
      Total CLB Flops:                 8 out of 128     6%
      4 input LUTs:                   11 out of 128     8%
      3 input LUTs:                    1 out of 64      1%

   Number of BUFGLSs                   1 out of 8      12%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (default)

Starting initial Placement phase.  REAL time: 4 secs 
Finished initial Placement phase.  REAL time: 4 secs 

Starting Constructive Placer.  REAL time: 4 secs 
Placer score = 4920
Placer score = 4170
Placer score = 3330
Finished Constructive Placer.  REAL time: 4 secs 

Writing design to file "map_lab.ncd".

Starting Optimizing Placer.  REAL time: 4 secs 
Optimizing  
Swapped 46 comps.
Xilinx Placer [1]   2220   REAL time: 4 secs 

Finished Optimizing Placer.  REAL time: 4 secs 

Writing design to file "map_lab.ncd".

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 

0 connection(s) routed; 56 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 4 secs 
Starting iterative routing. 
Routing active signals.
End of iteration 1 
56 successful; 0 unrouted; (0) REAL time: 4 secs 
Constraints are met. 
Routing PWR/GND nets.
Power and ground nets completely routed. 
Writing design to file "map_lab.ncd".
Starting cleanup 
Improving routing.
End of cleanup iteration 1 
56 successful; 0 unrouted; (0) REAL time: 5 secs 
Writing design to file "map_lab.ncd".
Total REAL time: 5 secs 
Total CPU  time: 3 secs 
End of route.  56 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 3 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 211


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.687 ns
   The Average Connection Delay on critical nets is:       0.000 ns
   The Average Clock Skew for this design is:              0.028 ns
   The Maximum Pin Delay is:                               4.277 ns
   The Average Connection Delay on the 10 Worst Nets is:   2.131 ns

   Listing Pin Delays by value: (ns)

    d <= 10    < d <= 20   < d <= 30   < d <= 40   < d <= 50    d > 50
   ---------   ---------   ---------   ---------   ---------   ---------
          56           0           0           0           0           0

Writing design to file "map_lab.ncd".


All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 4 secs 

PAR done.