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Xilinx TRACE, Version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Design file:              map_lab.ncd
Physical constraint file: map_lab.pcf
Device,speed:             xc4002xl,-09 (x1_0.37 1.22 PRELIMINARY)
Report level:             error report, limited to 3 items per constraint
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WARNING:bastw:170 - No timing constraints found, doing default enumeration.

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Timing constraint: Default period analysis
 126 items analyzed, 0 timing errors detected.
 Minimum period is   8.778ns.
 Maximum delay is  13.685ns.
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================================================================================
Timing constraint: Default net enumeration
 30 items analyzed, 0 timing errors detected.
 Maximum net delay is   4.277ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 126 paths, 30 nets, and 56 connections (100.0% coverage)

Design statistics:
   Minimum period:   8.778ns (Maximum frequency: 113.921MHz)
   Maximum combinational path delay:  13.685ns
   Maximum net delay:   4.277ns


Analysis completed Tue Oct 06 16:07:10 1998
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