-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Design file: design1sr2515.ncd Physical constraint file: design_1s.pcf Device,speed: xc4005e,-3 (x1_0.79 PRELIMINARY) Report level: verbose report, limited to 1 item per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: net FCLK period = 25; 1874 items analyzed, 38 timing errors detected. Minimum period is 28.428ns. -------------------------------------------------------------------------------- Slack: -3.428ns path VD1 to HSYNC- relative to 25.000ns delay constraint Path VD1 to HSYNC- contains 7 levels of logic: Path starting from Comp: CLB_R4C1.K (from FCLK) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R4C1.XQ Tcko 2.820R VD1 VD2 CLB_R4C3.G2 net 1.825R VD2 CLB_R4C3.Y Tilo 2.000R VIDTIM/VTIME2/NVRS VIDTIM/VTIME2/LX16_17/4.0/2.0 CLB_R3C4.F1 net 1.148R VIDTIM/VTIME2/LX16_17/4.0/2.0 CLB_R3C4.X Tilo 2.000R VIDTIM/VTIME2/LX0_17 VIDTIM/VTIME2/LX0_17 CLB_R3C5.F1 net 1.404R VIDTIM/VTIME2/LX0_17 CLB_R3C5.X Tilo 2.000R VIDTIM/NVDR VIDTIM/NVDR CLB_R1C3.G3 net 1.586R VIDTIM/NVDR CLB_R1C3.Y Tilo 2.000R VIDTIM/CSY- VIDTIM/CSYNC/M2 CLB_R1C3.F4 net 1.076R VIDTIM/CSYNC/M2 CLB_R1C3.X Tiho 4.310R VIDTIM/CSY- VIDTIM/NCS VIDTIM/CSY- P5.O net 1.659R VIDTIM/CSY- Took 4.600R HSYNC- HSYNC-.OUTFF ------------------------------------------------- Total (69.4% logic, 30.6% route) 28.428ns (to FCLK) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: offset = in 12 before comp CPUCLK; 44 items analyzed, 6 timing errors detected. Minimum allowable offset is 12.451ns. -------------------------------------------------------------------------------- Slack: -0.451ns path A1 to DBUS5 relative to 5.323ns delay constraint CPUCLK to DBUS5 and 12.000ns offset A1 to CPUCLK Data path A1 to DBUS5 contains 3 levels of logic: Path starting from Comp: P31.PAD To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- P31.I1 Tpid 2.520R A1 A1 REGSA/A1I CLB_R10C1.G4 net 2.445R REGSA/A1I CLB_R10C1.Y Tilo 2.000R DOEN- CTLWR P90.EC net 4.819R CTLWR Tecikd 5.990R DBUS5 CTL5 ------------------------------------------------- Total (59.1% logic, 40.9% route) 17.774ns (to FCLK) Clock path CPUCLK to DBUS5 contains 2 levels of logic: Path starting from Comp: P30.PAD To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- P30.CLKIN Tclkin 0.000R CPUCLK CPUCLK BUFGP_BL.I net 3.890R CPUCLK BUFGP_BL.O Tclk 0.000R $1I486 P90.IK net 1.433R FCLK ------------------------------------------------- Total (0.0% logic, 100.0% route) 5.323ns -------------------------------------------------------------------------------- 2 constraints not met. Timing summary: --------------- Timing errors: 44 Score: 40738 Constraints cover 1889 paths, 0 nets, and 750 connections (75.1% coverage) Design statistics: Minimum period: 28.428ns (Maximum frequency: 35.177MHz) Minimum input arrival time before clock: 12.451ns Analysis completed Wed Oct 15 17:31:28 1997 --------------------------------------------------------------------------------