-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.4.12 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Design file: design_1.ncd Physical constraint file: design_1.pcf Device,speed: xc4005e,-3 (x1_0.86 PRELIMINARY) Report level: verbose report, limited to 1 item per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: net FCLK period = 25; 1874 items analyzed, 2 timing errors detected. Minimum period is 28.428ns. -------------------------------------------------------------------------------- Slack: -3.428ns path VD1 to HSYNC- relative to 25.000ns delay constraint Path VD1 to HSYNC- contains 7 levels of logic: Path starting from Comp: CLB_R4C1.K (from FCLK) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R4C1.XQ Tcko 2.820R VD1 VD2 CLB_R4C3.G2 net (fanout=9) 1.825R VD2 CLB_R4C3.Y Tilo 2.000R VIDTIM/VTIME2/NVRS VIDTIM/VTIME2/LX16_17/4.0/2.0 CLB_R3C4.F1 net (fanout=1) 1.148R VIDTIM/VTIME2/LX16_17/4.0/2.0 CLB_R3C4.X Tilo 2.000R VIDTIM/VTIME2/LX0_17 VIDTIM/VTIME2/LX0_17 CLB_R3C5.F1 net (fanout=5) 1.404R VIDTIM/VTIME2/LX0_17 CLB_R3C5.X Tilo 2.000R VIDTIM/NVDR VIDTIM/NVDR CLB_R1C3.G3 net (fanout=3) 1.586R VIDTIM/NVDR CLB_R1C3.Y Tilo 2.000R VIDTIM/CSY- VIDTIM/CSYNC/M2 CLB_R1C3.F4 net (fanout=1) 1.076R VIDTIM/CSYNC/M2 CLB_R1C3.X Tiho 4.310R VIDTIM/CSY- VIDTIM/NCS VIDTIM/CSY- P5.O net (fanout=2) 1.659R VIDTIM/CSY- P5.OK Took 4.600R HSYNC- HSYNC-.OUTFF ------------------------------------------------- Total (19.730ns logic, 8.698ns route) 28.428ns (to FCLK) (69.4% logic, 30.6%% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: offset = in 12 before comp CPUCLK; 44 items analyzed, 6 timing errors detected. Minimum allowable offset is 13.794ns. -------------------------------------------------------------------------------- Slack: -1.794ns path A1 to DBUS5 relative to 5.271ns delay constraint CPUCLK to DBUS5 and 12.000ns offset A1 to CPUCLK Data path A1 to DBUS5 contains 3 levels of logic: Path starting from Comp: P31.PAD To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- P31.I1 Tpid 2.520R A1 A1 REGSA/A1I CLB_R10C1.G4 net (fanout=2) 2.445R REGSA/A1I CLB_R10C1.Y Tilo 2.000R DOEN- CTLWR P90.EC net (fanout=10) 6.110R CTLWR P90.IK Tecikd 5.990R DBUS5 CTL5 ------------------------------------------------- Total (10.510ns logic, 8.555ns route) 19.065ns (to FCLK) (59.1% logic, 40.9%% route) Clock path CPUCLK to DBUS5 contains 2 levels of logic: Path starting from Comp: P30.PAD To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- P30.CLKIN Tclkin 0.000R CPUCLK CPUCLK BUFGP_BL.I net (fanout=1) 3.890R CPUCLK BUFGP_BL.O Tclk 0.000R $1I486 P90.IK net (fanout=190) 1.381R FCLK ------------------------------------------------- Total (0.000ns logic, 5.271ns route) 5.271ns (0.0% logic, 100.0%% route) -------------------------------------------------------------------------------- 2 constraints not met. Timing summary: --------------- Timing errors: 8 Score: 8065 Constraints cover 2066 paths, 0 nets, and 859 connections (86.0% coverage) Design statistics: Minimum period: 28.428ns (Maximum frequency: 35.177MHz) Minimum input arrival time before clock: 12.451ns Analysis completed Wed Jan 21 16:25:55 1998 --------------------------------------------------------------------------------