ngdbuild -p xc4000e C:\Designs\lab1\design_1.xtf xc4000e.ngd ngdbuild: version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4000e C:\Designs\lab1\design_1.xtf xc4000e.ngd Launcher: Using rule XTF_RULE Launcher: design_1.ngo being compiled because it does not exist Launcher: Running xnf2ngd from C:\Designs\lab1\xproj\ver1\ Launcher: Executing xnf2ngd -p xc4000e -u "C:\Designs\lab1\design_1.xtf" "design_1.ngo" xnf2ngd: version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. using XNF gate model reading XNF file "C:/Designs/lab1/design_1.xtf" ... Writing NGO file "design_1.ngo" ... Launcher: "xnf2ngd" exited with an exit code of 0. Reading NGO file "C:/Designs/lab1/xproj/ver1/design_1.ngo" ... Reading component libraries for design expansion... Running Timing Specification DRC... Timing Specification DRC complete with no errors or warnings. Running Logical Design DRC... WARNING:basnu - clock net "PELFIFO/ADEB" has non-clock connections WARNING:basnu - clock net "PELFIFO/ADEB" drives no clock pins WARNING:basnu - clock net "VIDTIM/VCEN" has non-clock connections WARNING:basnu - clock net "VIDTIM/VCEN" drives no clock pins Logical Design DRC complete with 4 warning(s). NGDBUILD Design Results Summary: There were 4 Logical Design DRC warnings. 539 total blocks expanded. Writing NGD file "xc4000e.ngd" ... Writing NGDBUILD log file "xc4000e.bld"... NGDBUILD Done. map -p xc4005e-3-pq100 -o map.ncd ../xc4000e.ngd design_1.pcf map: version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Reading NGD file "../xc4000e.ngd"... Using target part "4005epq100-3". MAP xc4000e directives: Partname="xc4005e-3-pq100". No Guide File specified. No Guide Mode specified. Covermode="area". Coverlutsize=4. Coverfgsize=4. Perform logic replication. Pack CLBs to 97%. Processing logical timing constraints... Running general design DRC... The STARTUP component "$1I540" has been found with GSR signal "RSTI-". The STARTUP GSR pin is inverted. Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Processing global clock buffers... Optimizing... Removed Logic Summary: 19 block(s) clipped 1 block(s) removed 1 block(s) optimized away 19 signal(s) removed 1 signal(s) merged Design Summary: Number of warnings: 0 Number of errors: 0 Number of CLBs: 99 out of 196 Flops/latches: 105 4 input LUTs: 174 3 input LUTs: 41 Number of bonded IOBs: 70 out of 77 Number of clock IOBs: 1 out of 8 IO flops/latches: 53 Number of primary CLKs: 1 out of 4 Number of secondary CLKs: 2 out of 4 Number of RPM macros: 3 Number of STARTUPs: 1 ** Writing MDF file map.mdf for NCD output file map.ncd. ** Always use the MDF file with the guide NCD file for best results. Writing design file "map.ncd"... trce design_1.ncd design_1.pcf -v 1 -o design_1.twr Loading device database for application trce from file "design_1.ncd". "design_1" is an NCD, version 2.27, device xc4005e, package pq100, speed -3 Loading device for application trce from file '4005e.nph' in environment C:/XC3k5k. -------------------------------------------------------------------------------- Xilinx TRACE, Version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. Design file: design_1.ncd Physical constraint file: design_1.pcf Device,speed: xc4005e,-3 (x1_0.79 PRELIMINARY) Report level: verbose report, limited to 1 item per constraint -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 44 Score: 40738 Constraints cover 1889 paths, 0 nets, and 750 connections (75.1% coverage) Design statistics: Minimum period: 28.428ns (Maximum frequency: 35.177MHz) Minimum input arrival time before clock: 12.451ns Analysis completed Thu Oct 16 10:10:34 1997 -------------------------------------------------------------------------------- Total time: 16 secs