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Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              design_1.ncd
Physical constraint file: design_1.pcf
Device,speed:             xc4005e,-3 (x1_0.86  PRELIMINARY)
Report level:             verbose report, limited to 1 item per constraint
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================================================================================
Timing constraint: net FCLK period = 25;
 1896 items analyzed, 3 timing errors detected.
 Minimum period is  25.304ns.
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Slack:    -0.304ns path DBUS5 to PELD3 relative to
          25.000ns delay constraint

Path DBUS5 to PELD3 contains 4 levels of logic:
Path starting from Comp: P90.IK (from FCLK)
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
P90.I2               Tikri                 2.840R  DBUS5
                                                   CTL5
CLB_R4C7.F3          net (fanout=5)        1.621R  CTL5
CLB_R4C7.X           Tilo                  2.000R  $1N527
                                                   $1N527
BUFGS_TR.I           net (fanout=2)        7.810R  $1N527
BUFGS_TR.O           Tclk                  0.000R  PELFIFO/$1I341
P34.EC               net (fanout=40)       5.043R  PELFIFO/ADEB
P34.IK               Tecikd                5.990R  PELD3
                                                   PELFIFO/DI3
-------------------------------------------------
Total (10.830ns logic, 14.474ns route)    25.304ns (to FCLK)
      (42.8% logic, 57.2%% route)

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================================================================================
Timing constraint: offset = in 15 before comp CPUCLK;
 44 items analyzed, 0 timing errors detected.
 Minimum allowable offset is  14.681ns.
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Slack:     0.319ns path A1 to DBUS9 relative to
           5.317ns delay constraint CPUCLK to DBUS9 and
          15.000ns offset A1 to CPUCLK

Data path A1 to DBUS9 contains 3 levels of logic:
Path starting from Comp: P31.PAD
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
P31.I2               Tpid                  2.520R  A1
                                                   A1
                                                   REGSA/A1I
CLB_R5C6.F2          net (fanout=35)       4.840R  REGSA/A1I
CLB_R5C6.X           Tilo                  2.000R  CTLWR
                                                   CTLWR
P86.EC               net (fanout=10)       4.648R  CTLWR
P86.IK               Tecikd                5.990R  DBUS9
                                                   CTL9
-------------------------------------------------
Total (10.510ns logic, 9.488ns route)     19.998ns (to FCLK)
      (52.6% logic, 47.4%% route)

Clock path CPUCLK to DBUS9 contains 2 levels of logic:
Path starting from Comp: P30.PAD
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
P30.CLKIN            Tclkin                0.000R  CPUCLK
                                                   CPUCLK
BUFGP_BL.I           net (fanout=1)        3.890R  CPUCLK
BUFGP_BL.O           Tclk                  0.000R  $1I486
P86.IK               net (fanout=190)      1.427R  FCLK
-------------------------------------------------
Total (0.000ns logic, 5.317ns route)       5.317ns
      (0.0% logic, 100.0%% route)

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1 constraint not met.


Timing summary:
---------------

Timing errors: 3  Score: 609

Constraints cover 2090 paths, 0 nets, and 955 connections (81.6% coverage)


Design statistics:
   Minimum period:  25.304ns (Maximum frequency:  39.519MHz)
   Minimum input arrival time before clock:  14.681ns


Analysis completed Wed Jan 21 16:30:44 1998
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