Xilinx:cpld: version Trial
'(c)' Copyright 1996,1997,1998 Xilinx Inc.  All rights reserved.
Removing files calc_b.* in backup directory
Saving file calc_b.gyd to backup directory
Saving file calc_b.jed to backup directory
Saving file calc_b.rpt to backup directory
ngdbuild -p 9500XL  calc_b.edn
ngdbuild:  version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p 9500XL calc_b.edn 

Launcher: "calc_b.ngo" is up to date.
Reading NGO file "F:/xlnx/proj/calc_b/calc_b.ngo" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "calc_b.ucf" ...

Checking timing specifications ...

Checking expanded design ...
WARNING:basnu:113 - logical net "H5/ADDSUB1/OFL" has no load
WARNING:basnu:113 - logical net "H6/$I7/CEO" has no load
WARNING:basnu:113 - logical net "H6/$I7/TC" has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   3

Writing NGD file "calc_b.ngd" ...

Writing NGDBUILD log file "calc_b.bld"...

NGDBUILD done.

Optimizer/Partitioner:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Reading calc_b.ngd
Considering device XC9572XL-TQ100.
    Flattening design..
    Multi-level logic optimization.


..
    Timing optimization.................................................................................................
    Timing driven global resource optimization    General global resource optimization........
    Re-checking device resources ...
    Mapping a total of 66 equations into 4 function blocks..........................
Design calc_b has been optimized and fit into device XC9572XL-7-TQ100.
hplusas6 -i calc_b -s -o temp6

Fitter1:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
hprep6 -i temp6 -r jed -l calc_b.jed  -n calc_b

Programming File Generator:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
WARNING:rg5037 - Programming output for device type XC9572XL-7-TQ100 is not 
supported in this release. Call Xilinx Support for device availability.
tsim calc_b

Timing Simulation Interface:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Creating NGA for simulation.
taengine -f calc_b -l calc_b.tim


Timing Report Generator:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Path tracing ....................................
The number of paths traced: 6222.

Generating performance summary ...
Generating Pad-to-Pad delay section ...
Generating Clock-to-Output-Pad delay section ...
Generating Setup-To-Clock-At-Pad delay section ...
Generating Register-To-Register delay section ...
     Cycle time table for clock $Net00015_ ...
     Cycle time table for clock $Net00016_ ...

calc_b.tim has been created.