library IEEE;
use IEEE.std_logic_1164.all;

entity ptermhog is
    port (
        inhog1: in STD_LOGIC_VECTOR (6 downto 0);
       -- inhog2: in STD_LOGIC_VECTOR (7 downto 0);
        outhog: out STD_LOGIC
    );
end ptermhog;

architecture ptermhog_arch of ptermhog is
begin

  outhog <= (inhog1(0) and inhog1(1) and inhog1(2) and 
  inhog1(3) and inhog1(4) and inhog1(5) and inhog1(6));
--  (inhog1(1) and inhog1(2) and inhog1(3)) or 
--  (inhog1(2) and inhog1(3) and inhog1(4)) or
--  (inhog1(3) and inhog1(4) and inhog1(5)) or
--  (inhog1(4) and inhog1(5) and inhog1(6)) or
--  (inhog1(0) and inhog1(2) and inhog1(3)) or 
--  (inhog1(1) and inhog1(3) and inhog1(4)) or 
--  (inhog1(2) and inhog1(4) and inhog1(5)) or
--  (inhog1(3) and inhog1(5) and inhog1(6)) or 
--  (inhog1(4) and inhog1(6) and inhog1(1)) or 
--  (inhog1(5) and inhog1(1) and inhog1(2)) or

end ptermhog_arch;