ngdbuild -p xc9536-5-vq44 -uc d:\95prglab\j_cnt\j_cnt.ucf -dd .. d:\95prglab\j_cnt\j_cnt.edn j_cnt.ngd
ngdbuild:  version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc9536-5-vq44 -uc d:\95prglab\j_cnt\j_cnt.ucf -dd ..
d:\95prglab\j_cnt\j_cnt.edn j_cnt.ngd 

Launcher: Executing edif2ngd "d:\95prglab\j_cnt\j_cnt.edn"
"d:\95prglab\j_cnt\xproj\ver1\j_cnt.ngo"
edif2ngd:  version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
Writing the design to "d:/95prglab/j_cnt/xproj/ver1/j_cnt.ngo"...
Reading NGO file "d:/95prglab/j_cnt/xproj/ver1/j_cnt.ngo" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "d:/95prglab/j_cnt/j_cnt.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "j_cnt.ngd" ...

Writing NGDBUILD log file "j_cnt.bld"...

NGDBUILD done.

==================================================

hitop -f j_cnt.ngd -d j_cnt -s -l j_cnt.log -o j_cnt




Optimizer/Partitioner:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Reading j_cnt.ngd
Considering device XC9536-VQ44.
    Flattening design..
    Timing optimization
    Timing driven global resource optimization    General global resource optimization........
    Re-checking device resources ...
    Mapping a total of 8 equations into 2 function blocks........
Design j_cnt has been optimized and fit into device XC9536-5-VQ44.

==================================================

taengine -f j_cnt -l j_cnt.tim 


Timing Report Generator:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Path tracing .....
The number of paths traced: 57.

Generating performance summary ...
Generating Pad-to-Pad delay section ...
Generating Clock-to-Output-Pad delay section ...
Generating Setup-To-Clock-At-Pad delay section ...
Generating Register-To-Register delay section ...
     Cycle time table for clock $Net00001_ ...

j_cnt.tim has been created.

==================================================

tsim j_cnt.vm6 j_cnt.nga

Timing Simulation Interface:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Creating NGA for simulation.

==================================================

ngd2edif  -w j_cnt.nga time_sim.edn
ngd2edif:  version M1.5.19
Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
   writing only delay properties to EDIF file
   dedicated signals will be given local scope
   running NGD DRC ...
WARNING:basnu:110 - NOTE: This design contains the undriven net "PRLD" which
   you could drive during simulation to get valid results.
   writing EDIF file to "time_sim.edn" ...

==================================================

xcpy time_sim.edn d:\95prglab\j_cnt\time_sim.edn

==================================================

hplusas6 -i j_cnt -s -a -l j_cnt.log -o fe_temp

Fitter1:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.

==================================================

hprep6 -i fe_temp -r jed -a -l j_cnt.log -n j_cnt 

Programming File Generator:  version M1.5.19
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
Signature length is limited to 4 characters, using 'j_cn'.

==================================================

xcpy j_cnt.jed d:\95prglab\j_cnt\j_cnt.jed