XACT: version M1.5.19 Xilinx Inc. Fitter Report Design Name: j_cnt Fitting Status: Successful Date: 7-27-1998, 3:08PM **************************** Resource Summary **************************** Design Device Macrocells Product Terms Pins Name Used Used Used Used j_cnt XC9536-5-VQ44 8 /36 ( 22%) 8 /180 ( 4%) 9 /34 ( 26%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 0 0 | I/O : 8 20 Output : 0 0 | GCK/IO : 1 2 Bidirectional : 8 8 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 9 9 GLOBAL RESOURCES: Signal '$Net00001_' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 8 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 8 macrocells used (MC). End of Resource Summary ***************Resources Used by Successfully Mapped Logic****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Name Pt Used Mode Rate # Type Use $Net00013_ 1 1 FB2_14 STD FAST 22 I/O I/O $Net00014_ 1 1 FB2_15 STD FAST 21 I/O I/O $Net00015_ 1 1 FB2_16 STD FAST 20 I/O I/O $Net00016_ 1 1 FB2_17 STD FAST 19 I/O I/O $Net00017_ 1 1 FB1_17 STD FAST 18 I/O I/O $Net00018_ 1 1 FB1_16 STD FAST 16 I/O I/O $Net00019_ 1 1 FB1_15 STD FAST 14 I/O I/O $Net00020_ 1 1 FB1_14 STD FAST 13 I/O I/O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use $Net00001_ FB1_3 43 GCK/I/O GCK End of Resources Used by Successfully Mapped Logic *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 4 4 4 4 0/4 17 FB2 4 4 4 4 0/4 17 ---- ----- ----- ----- 8 8 0/8 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 4/32 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 40 I/O (unused) 0 0 0 5 FB1_2 41 I/O (unused) 0 0 0 5 FB1_3 43 GCK/I/O GCK (unused) 0 0 0 5 FB1_4 42 I/O (unused) 0 0 0 5 FB1_5 44 GCK/I/O (unused) 0 0 0 5 FB1_6 2 I/O (unused) 0 0 0 5 FB1_7 1 GCK/I/O (unused) 0 0 0 5 FB1_8 3 I/O (unused) 0 0 0 5 FB1_9 5 I/O (unused) 0 0 0 5 FB1_10 6 I/O (unused) 0 0 0 5 FB1_11 7 I/O (unused) 0 0 0 5 FB1_12 8 I/O (unused) 0 0 0 5 FB1_13 12 I/O $Net00020_ 1 0 0 4 FB1_14 STD 13 I/O I/O $Net00019_ 1 0 0 4 FB1_15 STD 14 I/O I/O $Net00018_ 1 0 0 4 FB1_16 STD 16 I/O I/O $Net00017_ 1 0 0 4 FB1_17 STD 18 I/O I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: $Net00016_.PIN 3: $Net00018_.PIN 4: $Net00019_.PIN 2: $Net00017_.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs $Net00020_ ...X.................................... 1 1 $Net00019_ ..X..................................... 1 1 $Net00018_ .X...................................... 1 1 $Net00017_ X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK/FCLK - Global clock O - Output GTS/FOE - Global 3state/output-enable (b) - Buried macrocell X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 4/32 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 39 I/O (unused) 0 0 0 5 FB2_2 38 I/O (unused) 0 0 0 5 FB2_3 36 GTS/I/O (unused) 0 0 0 5 FB2_4 37 I/O (unused) 0 0 0 5 FB2_5 34 GTS/I/O (unused) 0 0 0 5 FB2_6 33 GSR/I/O (unused) 0 0 0 5 FB2_7 32 I/O (unused) 0 0 0 5 FB2_8 31 I/O (unused) 0 0 0 5 FB2_9 30 I/O (unused) 0 0 0 5 FB2_10 29 I/O (unused) 0 0 0 5 FB2_11 28 I/O (unused) 0 0 0 5 FB2_12 27 I/O (unused) 0 0 0 5 FB2_13 23 I/O $Net00013_ 1 0 0 4 FB2_14 STD 22 I/O I/O $Net00014_ 1 0 0 4 FB2_15 STD 21 I/O I/O $Net00015_ 1 0 0 4 FB2_16 STD 20 I/O I/O $Net00016_ 1 0 0 4 FB2_17 STD 19 I/O I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: $Net00013_.PIN 3: $Net00015_.PIN 4: $Net00020_.PIN 2: $Net00014_.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs $Net00013_ ...X.................................... 1 1 $Net00014_ X....................................... 1 1 $Net00015_ .X...................................... 1 1 $Net00016_ ..X..................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK/FCLK - Global clock O - Output GTS/FOE - Global 3state/output-enable (b) - Buried macrocell X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. "$Net00013_" := /"$Net00020_".PIN "$Net00013_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00013_".PRLD = GND "$Net00014_" := "$Net00013_".PIN "$Net00014_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00014_".PRLD = GND "$Net00015_" := "$Net00014_".PIN "$Net00015_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00015_".PRLD = GND "$Net00016_" := "$Net00015_".PIN "$Net00016_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00016_".PRLD = GND "$Net00017_" := "$Net00016_".PIN "$Net00017_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00017_".PRLD = GND "$Net00018_" := "$Net00017_".PIN "$Net00018_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00018_".PRLD = GND "$Net00019_" := "$Net00018_".PIN "$Net00019_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00019_".PRLD = GND "$Net00020_" := "$Net00019_".PIN "$Net00020_".CLKF = "$Net00001_" ;FCLK/GCK "$Net00020_".PRLD = GND **************************** Device Pin Out **************************** Device : XC9536-5-VQ44 T T T T T T T V G T T I I I I I I I C N D I E E E E E E E C D O E -------------------------------- /33 32 31 30 29 28 27 26 25 24 23 \ TIE | 34 22 | $Net00013_ VCC | 35 21 | $Net00014_ TIE | 36 20 | $Net00015_ TIE | 37 19 | $Net00016_ TIE | 38 XC9536-5-VQ44 18 | $Net00017_ TIE | 39 17 | GND TIE | 40 16 | $Net00018_ TIE | 41 15 | VCC TIE | 42 14 | $Net00019_ $Net00001_ | 43 13 | $Net00020_ TIE | 44 12 | TIE \ 1 2 3 4 5 6 7 8 9 10 11 / -------------------------------- T T T G T T T T T T T I I I N I I I I D M C E E E D E E E E I S K Legend : TIE = Tie pin to GND or board trace driven to valid logic level VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : XC9536-5-VQ44 Use Timing Constraints : ON Ignore Assignments In Design File : OFF Create Programmable Ground Pins : OFF Use Advanced Fitting : ON Use Local Feedback : ON Use Pin Feedback : ON Default Power Setting : STD Default Output Slew Rate : FAST Guide File Used : NONE Multi Level Logic Optimization : ON Timing Optimization : ON Power/Slew Optimization : OFF High Fitting Effort : ON Automatic Wire-ANDing : ON Xor Synthesis : ON D/T Synthesis : ON Use Boolean Minimization : ON Use Global Nets : ON Collapsing pterm limit : 20 Collapsing input limit : 36