Performance Summary Report
                           --------------------------

Design:     j_cnt
Device:     XC9536-5-VQ44 
Program:    Timing Report Generator:  version M1.5.19
Date:       Mon Jul 27 15:08:24 1998

Performance Summary: 

Clock net '$Net00001_' path delays:

Clock Pad to Output Pad (tCO)             :          4.5ns (1 macrocell levels)
Clock Pad '$Net00001_' to Output Pad '$Net00020_'                         (GCK)

Clock to Setup (tCYC)                     :          9.0ns (1 macrocell levels)
Clock to Q, net 'J_CNT_OUT<7>.Q' to DFF Setup(D) at 'J_CNT_OUT<0>.D'        (GCK)
Target FF drives output net 'J_CNT_OUT<0>.Q'

Setup to Clock at the Pad (tSU)           :          4.5ns (0 macrocell levels)
Data signal '$Net00020_' to DFF D input Pin at 'J_CNT_OUT<0>.D'
Clock pad '$Net00001_'                                                    (GCK)

                          Minimum Clock Period: 9.0ns
                     Maximum Internal Clock Speed: 111.1Mhz
                            (Limited by Cycle Time)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From         $
 \             N
  \            e
   \           t
    \          0
     \         0
      \        0
       \       0
        \      1
         \     _
  To      \------

$Net00013_   4.5
$Net00014_   4.5
$Net00015_   4.5
$Net00016_   4.5
$Net00017_   4.5
$Net00018_   4.5
$Net00019_   4.5
$Net00020_   4.5

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From         $
 \             N
  \            e
   \           t
    \          0
     \         0
      \        0
       \       0
        \      1
         \     _
  To      \------

$Net00013_   4.5
$Net00014_   4.5
$Net00015_   4.5
$Net00016_   4.5
$Net00017_   4.5
$Net00018_   4.5
$Net00019_   4.5
$Net00020_   4.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                              (Clock: $Net00001_)

\ From             J     J     J     J     J     J     J     J
 \                 _     _     _     _     _     _     _     _
  \                C     C     C     C     C     C     C     C
   \               N     N     N     N     N     N     N     N
    \              T     T     T     T     T     T     T     T
     \             _     _     _     _     _     _     _     _
      \            O     O     O     O     O     O     O     O
       \           U     U     U     U     U     U     U     U
        \          T     T     T     T     T     T     T     T
         \         <     <     <     <     <     <     <     <
          \        0     1     2     3     4     5     6     7
           \       >     >     >     >     >     >     >     >
            \      .     .     .     .     .     .     .     .
             \     Q     Q     Q     Q     Q     Q     Q     Q
  To          \------------------------------------------------

J_CNT_OUT<0>.D                                             9.0
J_CNT_OUT<1>.D   9.0                                          
J_CNT_OUT<2>.D         9.0                                    
J_CNT_OUT<3>.D               9.0                              
J_CNT_OUT<4>.D                     9.0                        
J_CNT_OUT<5>.D                           9.0                  
J_CNT_OUT<6>.D                                 9.0            
J_CNT_OUT<7>.D                                       9.0      

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.