-- Xilinx XPort Language Converter, Version 2.1 (010) -- -- AHDL Design Source: sdramctl.tdf -- VHDL Design Output: sdramctl.vhd -- Created 20-Aug-1997 03:21 PM -- -- (c) 1997, Xilinx, Inc. All Rights Reserved. -- Xilinx makes no warranty, expressed or implied, with respect to -- the operation and/or functionality of the converted output files. -- -- Some names could not be written out to VHDL as they were -- in the source, and have been changed: -- -- AHDL VHDL -- ==== ==== -- cs__5 cs_5 -- cs__4 cs_4 -- cs__3 cs_3 -- cs__2 cs_2 -- cs__1 cs_1 -- ras__5 ras_5 -- ras__4 ras_4 -- ras__3 ras_3 -- ras__2 ras_2 -- ras__1 ras_1 -- cas__5 cas_5 -- cas__4 cas_4 -- cas__3 cas_3 -- cas__2 cas_2 -- cas__1 cas_1 -- we__5 we_5 -- we__4 we_4 -- we__3 we_3 -- we__2 we_2 -- we__1 we_1 -- cycrun_.q cycrun_q -- cycrun_.d cycrun_d -- we_ we -- cas_ cas -- ras_ ras -- cs_ cs -- cycrun_ cycrun -- ready_ ready_1 -- be_ be -- blast_ blast_1 -- ads_ ads_1 -- resetus_ resetus Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity sdramctl is -- -- unsynchronized reset and refresh request -- Port ( clk, resetus, refrqus, ads_1, wr, blast_1: in std_logic; be: in std_logic_vector(3 downto 0); ain31, ain30, ain29, ain28: in std_logic; ain: in std_logic_vector(25 downto 2); mrssel, cl1, dramsize: in std_logic; ready_1, cycrun: buffer std_logic; dqm: buffer std_logic_vector(3 downto 0); cs, ras, cas, we: buffer std_logic; aout: buffer std_logic_vector(13 downto 0) ); end sdramctl; architecture sdramctl_behav of sdramctl is -- -- xx_next: Setup value of xx for next rising clock edge -- xxlast: The value of xx last clock -- -- -- dopre: Execute PALL command this cycle -- donop: Execute NOP this cycle and next -- resetlast: synchronized reset delayed by 1 clock -- ready: Output value of READY -- refrq: If not ref_block, execute a REF command this cycle, -- block ADS -- cycrun: True middle of cycle following ADS until middle of -- cycle following BLAST & READY -- inhost: ACT done, goes false on clock following BLAST & READY -- casel: Select column address this cycle, -- During PALL cycle, selects hia to signal precharge type -- domrs: Execute MRS command this cycle -- ads_block: Prevent ADS_ from starting a memory cycle this clock -- adspend: Held value of ADS_ if ads_block held off ADS_ -- ref_block: Prevent refrq_ from starting a refresh cycle this clock -- signal regca: std_logic_vector(1 downto 0); signal regca_d: std_logic_vector(1 downto 0); signal regca_q: std_logic_vector(1 downto 0); signal dqm3_2, dqm3_1, dqm2_2, dqm2_1, dqm1_2, dqm1_1, dqm0_2, dqm0_1, cs_5, cs_4, cs_3, cs_2, cs_1, ras_5, ras_4, ras_3, ras_2, ras_1, cas_5, cas_4, cas_3, cas_2, cas_1, we_5, we_4, we_3, we_2, we_1, hia_2, hia_1, inhost_next_2, inhost_next_1, casel_next_3, casel_next_2, casel_next_1, dopre_next_2, dopre_next_1, ready_next_2, ready_next_1, ads_block_next_5, ads_block_next_4, ads_block_next_3, ads_block_next_2, ads_block_next_1, cycrun_next_2, cycrun_next_1, ref_block_next_6, ref_block_next_5, ref_block_next_4, ref_block_next_3, ref_block_next_2, ref_block_next_1, donop_next_2, donop_next_1, gnd, vcc, ref_block_q, ref_block_d, ref_block, adspend_q, adspend_d, adspend, ads_block_q, ads_block_d, ads_block, domrs_q, domrs_d, domrs, casel_q, casel_d, casel, inhost_q, inhost_d, inhost, cycrun_q, cycrun_d, cycrun_hold_q, cycrun_hold_d, cycrun_hold, resets2_q, resets2_d, resets2, resets1_q, resets1_d, resets1, refrqlast_q, refrqlast_d, refrqlast, refrqs2_q, refrqs2_d, refrqs2, refrqs1_q, refrqs1_d, refrqs1, refrq_q, refrq_d, refrq, donop_q, donop_d, donop, ready_q, ready_d, ready, resetlast_q, resetlast_d, resetlast, inhostlast_q, inhostlast_d, inhostlast, dopre_q, dopre_d, dopre, donop_next, ref_block_next, cycrun_next, domrs_next, ads_block_next, refrq_next, inhostlast_next, ready_next, dopre_next, casel_next, inhost_next, reset, ads, blast, rd, hia: std_logic; Function to_std_logic(X: in Boolean) return Std_Logic is variable ret : std_logic; begin if x then ret := '1'; else ret := '0'; end if; return ret; end to_std_logic; -- sizeIt replicates a value to an array of specific length. Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is variable rep: std_logic_vector( len-1 downto 0); begin for i in rep'range loop rep(i) := a; end loop; return rep; end sizeIt; begin -- Register Section -- -- Comment from eliminated register control equation at source line: 107 -- must be negative edge triggered! cycrun <= cycrun_q; process (clk) begin if clk'event and clk='0' then cycrun_q <= cycrun_d; end if; end process; process (clk) begin if clk'event and clk='1' then (dopre_q, inhostlast_q, resetlast_q, ready_q, donop_q, refrq_q, refrqs1_q, refrqs2_q, refrqlast_q, resets1_q, resets2_q, regca_q(1), regca_q(0), cycrun_hold_q, inhost_q, casel_q, domrs_q, ads_block_q, adspend_q, ref_block_q) <= std_logic_vector'(dopre_d & inhostlast_d & resetlast_d & ready_d & donop_d & refrq_d & refrqs1_d & refrqs2_d & refrqlast_d & resets1_d & resets2_d & regca_d(1) & regca_d(0) & cycrun_hold_d & inhost_d & casel_d & domrs_d & ads_block_d & adspend_d & ref_block_d); end if; end process; -- Start of original equations -- -- refresh request synchronizer -- refrqs1_d <= refrqus; refrqs2_d <= refrqs1_q; refrqlast_d <= refrqs2_q; -- -- reset synchronizer -- resets1_d <= not resetus; resets2_d <= resets1_q; resetlast_d <= resets2_q; reset <= resets2_q; blast <= not blast_1; ads <= not ads_1; ready_1 <= not ready_q; rd <= not wr; process (reset, resetlast_q, vcc) begin (casel_next_1, dopre_next_1, ref_block_next_1) <= std_logic_vector'("000"); -- -- at end of reset do precharge -- if ((not reset) and resetlast_q)='1' then casel_next_1 <= vcc; dopre_next_1 <= vcc; ref_block_next_1 <= vcc; end if; end process; process (dopre_q) begin (cs_1, ras_1, cas_1, we_1, hia_1) <= std_logic_vector'("11110"); if (dopre_q)='1' then (cs_1, ras_1, cas_1, we_1, hia_1) <= std_logic_vector'("00101"); end if; end process; process (inhost_q, blast, ready_q, rd, cl1, inhostlast_q, gnd, be, vcc) begin (dopre_next_2, ads_block_next_1, inhostlast_next, casel_next_2, ref_block_next_2, inhost_next_1, cycrun_next_1, cs_2, ras_2, cas_2, we_2, hia_2, dqm3_1, dqm2_1, dqm1_1, dqm0_1, ready_next_1) <= std_logic_vector'("00000001111011110"); if (inhost_q)='1' then if (blast and ready_q)='1' then if (rd)='1' then (cs_2, ras_2, cas_2, we_2, hia_2) <= std_logic_vector'("00101"); else (cs_2, ras_2, cas_2, we_2, hia_2) <= std_logic_vector'("01000"); dopre_next_2 <= vcc; ref_block_next_2 <= vcc; casel_next_2 <= vcc; (dqm3_1, dqm2_1, dqm1_1, dqm0_1) <= be; ads_block_next_1 <= vcc; end if; else inhostlast_next <= vcc; casel_next_2 <= vcc; ref_block_next_2 <= vcc; inhost_next_1 <= vcc; cycrun_next_1 <= vcc; if (rd)='1' then if (cl1 or inhostlast_q)='1' then ready_next_1 <= vcc; end if; (dqm3_1, dqm2_1, dqm1_1, dqm0_1) <= sizeIt(gnd,4); (cs_2, ras_2, cas_2, we_2, hia_2) <= std_logic_vector'("01010"); else (cs_2, ras_2, cas_2, we_2, hia_2) <= std_logic_vector'("01000"); (dqm3_1, dqm2_1, dqm1_1, dqm0_1) <= be; ready_next_1 <= vcc; end if; end if; end if; end process; process (donop_q, vcc) begin (ads_block_next_2, ref_block_next_3) <= std_logic_vector'("00"); if (donop_q)='1' then ads_block_next_2 <= vcc; ref_block_next_3 <= vcc; end if; end process; process (refrq_q, ref_block_q, vcc) begin (ads_block_next_3, refrq_next, donop_next_1, ref_block_next_4, cs_3, ras_3, cas_3, we_3) <= std_logic_vector'("00001111"); if (refrq_q)='1' then ads_block_next_3 <= vcc; if (ref_block_q)='1' then refrq_next <= vcc; else donop_next_1 <= vcc; ref_block_next_4 <= vcc; (cs_3, ras_3, cas_3, we_3) <= std_logic_vector'("0001"); end if; end if; end process; process (refrqs2_q, refrqlast_q, refrq_next, vcc) begin (refrq_d, ads_block_next_4) <= std_logic_vector'("-0"); if ((refrqs2_q and (not refrqlast_q)) or refrq_next)='1' then refrq_d <= vcc; ads_block_next_4 <= vcc; end if; end process; process (ads, ain28, ain29, ain30, ain31, adspend_q, ads_block_q, mrssel, wr, vcc, gnd) begin (cycrun_next_2, adspend_d, domrs_next, cs_4, ras_4, cas_4, we_4, casel_next_3, inhost_next_2, ref_block_next_5, ready_next_2, dqm3_2, dqm2_2, dqm1_2, dqm0_2) <= std_logic_vector'("000111100001111"); if ((to_std_logic(ads='1' and std_logic_vector'(ain31 & ain30 & ain29 & ain28) = "0001")) or adspend_q)='1' then cycrun_next_2 <= vcc; if (ads_block_q)='1' then adspend_d <= vcc; elsif (mrssel)='1' then ready_next_2 <= vcc; domrs_next <= vcc; ref_block_next_5 <= vcc; else (cs_4, ras_4, cas_4, we_4) <= std_logic_vector'("0011"); casel_next_3 <= vcc; inhost_next_2 <= vcc; ref_block_next_5 <= vcc; if (wr)='1' then ready_next_2 <= vcc; else (dqm3_2, dqm2_2, dqm1_2, dqm0_2) <= sizeIt(gnd,4); end if; end if; end if; end process; process (domrs_q, vcc, casel_q, dramsize, regca_q, hia, ain) variable stdVec2: std_logic_vector(1 downto 0); begin aout <= "00000000000000"; (ads_block_next_5, ref_block_next_6, donop_next_2, cs_5, ras_5, cas_5, we_5) <= std_logic_vector'("0001111"); if (domrs_q)='1' then ads_block_next_5 <= vcc; ref_block_next_6 <= vcc; donop_next_2 <= vcc; (cs_5, ras_5, cas_5, we_5) <= std_logic_vector'("0000"); aout <= ain(15 downto 2); else -- -- aout[ 13..12 ] for cases 0 and 1 are don't care -- they are left at ain[ 23..22 ] to simplify the logic -- since they are needed for cases 2 and 3 -- -- 16 meg SDRAMs -- 64 meg SDRAMs stdVec2 := std_logic_vector'(dramsize & casel_q); case stdVec2 is when "00" => aout <= ain(23 downto 10); when "01" => aout <= std_logic_vector'(ain(23) & ain(22) & ain(21) & hia & ain(23 downto 22) & ain(9 downto 4) & regca_q); when "10" => aout <= ain(23 downto 10); when "11" => aout <= std_logic_vector'(ain(23) & ain(22) & ain(21) & hia & ain(25 downto 24) & ain(9 downto 4) & regca_q); when others => end case; stdVec2 := (others=>'0'); -- no storage needed end if; end process; process (inhost_q, regca_q, ain) begin regca_d <= std_logic_vector'("--"); if (inhost_q)='1' then regca_d <= std_logic_vector'(unsigned(regca_q) + unsigned'("01")); else regca_d <= ain(3 downto 2); end if; end process; cycrun_hold_d <= cycrun_next and (not reset); cycrun_d <= not cycrun_hold_q; ready_d <= ready_next and (not reset); inhostlast_d <= inhostlast_next and (not reset); domrs_d <= domrs_next and (not reset); ads_block_d <= ads_block_next and (not reset); donop_d <= donop_next and (not reset); dopre_d <= dopre_next and (not reset); ref_block_d <= ref_block_next and (not reset); inhost_d <= inhost_next and (not reset); casel_d <= casel_next and (not reset); -- Assignments added to explicitly combine the -- effects of multiple drivers in the source donop_next <= donop_next_1 or donop_next_2; ref_block_next <= ref_block_next_1 or ref_block_next_2 or ref_block_next_3 or ref_block_next_4 or ref_block_next_5 or ref_block_next_6; cycrun_next <= cycrun_next_1 or cycrun_next_2; ads_block_next <= ads_block_next_1 or ads_block_next_2 or ads_block_next_3 or ads_block_next_4 or ads_block_next_5; ready_next <= ready_next_1 or ready_next_2; dopre_next <= dopre_next_1 or dopre_next_2; casel_next <= casel_next_1 or casel_next_2 or casel_next_3; inhost_next <= inhost_next_1 or inhost_next_2; hia <= hia_1 or hia_2; we <= we_1 and we_2 and we_3 and we_4 and we_5; cas <= cas_1 and cas_2 and cas_3 and cas_4 and cas_5; ras <= ras_1 and ras_2 and ras_3 and ras_4 and ras_5; cs <= cs_1 and cs_2 and cs_3 and cs_4 and cs_5; dqm(0) <= dqm0_1 and dqm0_2; dqm(1) <= dqm1_1 and dqm1_2; dqm(2) <= dqm2_1 and dqm2_2; dqm(3) <= dqm3_1 and dqm3_2; -- Define power signal(s) vcc <= '1'; gnd <= '0'; end sdramctl_behav;