library IEEE;
use IEEE.std_logic_1164.all;
--use SYNOPSYS.std_logic_arith.all;
--use IEEE.std_logic_arith.all;

entity TOP_SDRAM_2 is
	Port (	CLOCK			: IN STD_LOGIC;
		WRITE_IN		: IN STD_LOGIC;
		RESET			: IN STD_LOGIC;
		ADDRESS_BUS_IN_IN	: IN STD_LOGIC_VECTOR (23 downto 0);
		DATA_BUS_IN		: IN STD_LOGIC_VECTOR (15 downto 0);
		CS			: OUT  STD_LOGIC;
		RAS			: OUT   STD_LOGIC;
		CAS			: OUT   STD_LOGIC;
		WE			: OUT   STD_LOGIC;
	      ADDRESS_BUS_OUT		: OUT STD_LOGIC_VECTOR (11 downto 0)
	);
end TOP_SDRAM_2;

architecture BEHAVIORAL of TOP_SDRAM_2 is

type STATE_TYPE is ( IDLE,  MODE_PRE_CHARGE,  MODE_REG, WRITE_REG_DATA, REFRESH_SDRAM, ROW_ACTIVATE, READ_DATA, WRITE_DATA, DATA_PRE_CHARGE );
  signal  CURRENT_STATE, NEXT_STATE: STATE_TYPE;
  signal  NEXT_CS, NEXT_RAS, NEXT_CAS, NEXT_WE: STD_LOGIC;
  signal  NEXT_ADDRESS_BUS: STD_LOGIC_VECTOR (11 downto 0);
  signal  DATA_BUS: STD_LOGIC_VECTOR (15 downto 0);
  signal  ADDRESS_BUS_IN : STD_LOGIC_VECTOR (23 downto 0);
  signal  CHIP_SELECT, REFRESH, PROGRAM, WRITE:  STD_LOGIC;

begin

-- ALL SIGNALS ASSERTED HIGH (TRUE)

COMBIN: PROCESS (CURRENT_STATE, CHIP_SELECT, WRITE_IN, REFRESH,
			PROGRAM, ADDRESS_BUS_IN, DATA_BUS_IN, RESET,
			CLOCK, WRITE, ADDRESS_BUS_IN, DATA_BUS)

	VARIABLE      cnt	:  INTEGER  RANGE  0 to 2048;

begin
	NEXT_STATE <= CURRENT_STATE;
	NEXT_CS        <='0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS  <="111111111111";

case CURRENT_STATE is

	when  IDLE  =>
		if(CHIP_SELECT = '1' and WRITE = '1' and REFRESH = '0' 
		and PROGRAM = '1') then
	NEXT_STATE   <= MODE_PRE_CHARGE;
	NEXT_CS         <='1';
	NEXT_RAS        <='1';
	NEXT_CAS        <='0';
	NEXT_WE         <='1';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

elsif (REFRESH = '1') then
	NEXT_STATE  <= REFRESH_SDRAM;
	NEXT_CS       <='1';
	NEXT_RAS      <='1';
	NEXT_CAS      <='1';
	NEXT_WE       <='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

elsif (CHIP_SELECT = '1' and REFRESH = '0' and PROGRAM = '0') then
	NEXT_STATE <= ROW_ACTIVATE;
	NEXT_CS        <=  '1';
	NEXT_RAS       <=  '1';
	NEXT_CAS       <=  '0';
	NEXT_WE        <=  '0';
	NEXT_ADDRESS_BUS  <=ADDRESS_BUS_IN (23 downto 12);

else
	NEXT_STATE	<= IDLE;
	NEXT_CS		<='0';
	NEXT_RAS	<='0';
	NEXT_CAS	<='0';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

end if;

when REFRESH_SDRAM =>

	NEXT_STATE	<= DATA_PRE_CHARGE;
	NEXT_CS		<='1';
	NEXT_RAS	<='1';
	NEXT_CAS	<='0';
	NEXT_WE		<='1';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);


when  MODE_PRE_CHARGE =>

if (CHIP_SELECT = '1' and WRITE = '1' and REFRESH = '0' and PROGRAM = '1') then

	NEXT_STATE	<= MODE_REG;
	NEXT_CS		<='1';
	NEXT_RAS	<='1';
	NEXT_CAS	<='1';
	NEXT_WE		<='1';
	NEXT_ADDRESS_BUS  <= DATA_BUS  (11 downto 0);

elsif (REFRESH = '1') then

	NEXT_STATE	<= REFRESH_sdram;
	NEXT_CS		<='1';
	NEXT_RAS	<='1';
	NEXT_CAS	<='1';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

	NEXT_STATE	<= IDLE;
	NEXT_CS		<= '0';
	NEXT_RAS	<='0';
	NEXT_CAS	<='0';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <=  ADDRESS_BUS_IN (23 downto 12);

end if;

when  MODE_REG =>

if (CHIP_SELECT = '1' and WRITE = '1' and REFRESH = '0' and PROGRAM = '1') then

	NEXT_STATE	<= WRITE_REG_DATA;
	NEXT_CS		<='1';
	NEXT_RAS	<='0';
	NEXT_CAS	<='1';
	NEXT_WE		<='1';
	NEXT_ADDRESS_BUS  <= DATA_BUS (11 downto 0);

elsif (REFRESH = '1') then

	NEXT_STATE	<= REFRESH_SDRAM;
	NEXT_CS		<='1';
	NEXT_RAS	<='1';
	NEXT_CAS	<='1';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

else

	NEXT_STATE	<= IDLE;
	NEXT_CS		<='0';
	NEXT_RAS	<='0';
	NEXT_CAS	<='0';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12);

end if;

when WRITE_REG_DATA =>

if (REFRESH = '1') then

	NEXT_STATE	<= REFRESH_SDRAM;
	NEXT_CS		<='1';
	NEXT_RAS	<='1';
	NEXT_CAS	<='1';
	NEXT_WE		<='0';
	NEXT_ADDRESS_BUS  <= ADDRESS_BUS_IN (23 downto 12); 

else

	NEXT_STATE <= IDLE;
	NEXT_CS        <='0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);
end if;

when  ROW_ACTIVATE  =>

if (CHIP_SELECT = '1' and WRITE = '1' and REFRESH = '0' and PROGRAM = '0') then

	NEXT_STATE <= WRITE_DATA;
	NEXT_CS        <='1';
	NEXT_RAS       <='0';
	NEXT_CAS       <='1';
	NEXT_WE        <='1';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

elsif (CHIP_SELECT = '1' and WRITE = '0' and REFRESH = '0'
       and PROGRAM = '0') then

	NEXT_STATE <= READ_DATA;
	NEXT_CS        <='1';
	NEXT_RAS       <='1';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

elsif (REFRESH = '1') then

	NEXT_STATE <=REFRESH_SDRAM;
	NEXT_CS        <='1';
	NEXT_RAS       <='1';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

else

	NEXT_STATE <= IDLE;
	NEXT_CS        <= '0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

end if;

when  WRITE_DATA =>

if (CHIP_SELECT = '1' and REFRESH = '0' and PROGRAM ='0') then

	NEXT_STATE <=IDLE;
	NEXT_CS        <='1';
	NEXT_RAS       <='0';
	NEXT_CAS       <='1';
	NEXT_WE        <='1';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (11 downto 0);

elsif (REFRESH = '1') then

	NEXT_STATE <= REFRESH_SDRAM;
	NEXT_CS        <='1';
	NEXT_RAS       <='1';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

else

	NEXT_STATE <= IDLE;
	NEXT_CS        <='0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

end if;

when  READ_DATA =>

if  (CHIP_SELECT ='1' and REFRESH = '0' and PROGRAM ='0') then

	NEXT_STATE <=DATA_PRE_CHARGE;
	NEXT_CS        <='1';
	NEXT_RAS       <='0';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (11 downto 0);

elsif (REFRESH = '1')  then

	NEXT_STATE <= REFRESH_SDRAM;
	NEXT_CS        <='1';
	NEXT_RAS       <='1';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

else

	NEXT_STATE <=  IDLE;
	NEXT_CS        <='0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

end if;

when  DATA_PRE_CHARGE =>

if  (REFRESH = '1') then

	NEXT_STATE <=REFRESH_SDRAM;
	NEXT_CS        <= '1';
	NEXT_RAS       <='1';
	NEXT_CAS       <='1';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

else

	NEXT_STATE <= IDLE;
	NEXT_CS        <= '0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

end if;

when others  =>

	NEXT_STATE <= IDLE;
	NEXT_CS        <= '0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0';
	NEXT_WE        <='0';
	NEXT_ADDRESS_BUS <= ADDRESS_BUS_IN (23 downto 12);

end case;

if  RESET = '1' then

	NEXT_STATE <= IDLE;
	NEXT_CS        <='0';
	NEXT_RAS       <='0';
	NEXT_CAS       <='0'; 
	NEXT_WE        <='0'; 
	ADDRESS_BUS_OUT <= "111111111111";

elsif CLOCK'event and CLOCK = '1' then

	CURRENT_STATE   <= NEXT_STATE;
	CS      	    <= NEXT_CS;
	RAS             <= NEXT_RAS;
	CAS             <= NEXT_CAS;
	WE              <= NEXT_WE;
	ADDRESS_BUS_OUT <= NEXT_ADDRESS_BUS; 

--Latch all inputs

WRITE <=WRITE_IN;
ADDRESS_BUS_IN  <= ADDRESS_BUS_IN_IN;
DATA_BUS <= DATA_BUS_IN;

cnt := cnt+1;

	if (cnt = 2048)  then
		REFRESH <= '1';
		cnt  := 0;
	else REFRESH <='0';

	end if;

end if;

	if (ADDRESS_BUS_IN (23) = '1' and ADDRESS_BUS_IN (22) = '1' and
    	    ADDRESS_BUS_IN (21) = '1' and ADDRESS_BUS_IN (20) = '1' and
   	    ADDRESS_BUS_IN (19) = '1')  then

		CHIP_SELECT <= '1';
		else CHIP_SELECT <= '0';
	end if;

	if (ADDRESS_BUS_IN (23) = '1' and ADDRESS_BUS_IN (22) = '1' and
    	    ADDRESS_BUS_IN (21) = '1' and ADDRESS_BUS_IN (20) = '1' and
   	    ADDRESS_BUS_IN (19) = '1' and ADDRESS_BUS_IN (18) = '1')  then


		PROGRAM <= '1';
		else  PROGRAM <= '0';
	end if;
end PROCESS;

end BEHAVIORAL;
configuration CFG_TOP_SDRAM_2_BEHAVIORAL of TOP_SDRAM_2 is
     for  BEHAVIORAL
end for;

end CFG_TOP_SDRAM_2_BEHAVIORAL;