XC4000XV Product Highlights

Introducing:

The first 0.25 micron FPGA!
The first 500,000 gate FPGA Family!
The first 2.5V FPGA!

The XC4000XV features a leading edge 0.25 micron family of four members that will deliver up to 500,000 system gates by mid-1998, ranging in density from 10,982 to 20,102 logic cells with the XC40125XV device available NOW! The XC4000XV features industry-leading system performance of over 100 MHz while minimizing power consumption in today's high performance systems. The 2.5-volt XC4000XV family extends and builds on the successes of the 5-volt XC4000 and the 3-volt XC4000XL series by reaching new heights in process technology, density, and performance.

Up to 500,000 Gates

Four family members
10,982 to 20,102 logic cells (4-input look-up-table and flip-flop)
Up to 500,000 system level gates
Up to 448 user I/O pins
XC40125XV available NOW!

Features

Select-RAM memory, fully synchronous timing, true dual-port capability
IEEE 1149.1-compatible boundary scan logic
Internal 3-state bus capability
12/24 mA sink current per output
Wide edge decoders

Supply Voltage and Power Consumption

The XC4000XV features 2.5-volt internal operation with 3.3-volt I/Os to allow optimal performance and compatibility with existing voltage standards. Combined with the Xilinx segmented routing architecture, the XC4000XV family delivers on extremely low power consumption with higher performance, higher utilization and higher reliability.

0.25 Micron Process Technology

The XC4000XV family is the first to deliver programmable logic using 0.25 micron technology, leading the logic industry into the most advanced semiconductor manufacturing process. In partnership with United Microelectronics Corporation (UMC), the Xilinx XC40125XV is the first logic device which incorporates 25 million transistors in a single piece of silicon - more than three times that of today's highest performance microprocessors, such as the Intel Pentium II with 7.5 million transistors.

The XV family is also the first to incorporate a 0.25 micron CMOS process with dual-gate oxide and five metal layers. UMC and Xilinx have jointly developed 0.25 micron FPGA technology. The Xilinx partnerships with industry leading manufacturingpartners has directly aided in the delivery of advanced processes, and builds on a five year road map that will culminate in the availability of 2,000,000 gate FPGAs in the year 2000.

Architectural Advantages and Family Highlights

The XC4000XV family is an advanced implementation of the XC4000XL architecture with Xilinx segmented routing and distributed RAM. These features make an ideal platform for implementing cores. Local routing resources in short, segmented routing allow for predictable performance regardless of how much logic is employed and how large the device is. With non-segmented interconnect architectures, cores will slow down unpredictably as surrounding logic is added or as larger devices are required. Performance predictability is a requirement for designs with intellectual property because designers choose cores independently of device density and expect performance to remain the same as the design evolves. Further, due to footprint-compatibility advantages, current XC4000XL customers can easily and immediately upgrade to the higher-density XC4000XV products.

Availability

The XC40125XV device is now available in Ball Grid Array (BGA) and Pin Grid Array (PGA) packages.

Device Logic Cells RAM Bits Typical Gate Range (Logic + RAM) Availability

XC40125 10,982 147,968 80,000 - 265,000 Now!

XC40150 12,312 165,888 100,000 - 300,000 Q3 98

XC40200 16,758 225,792 130,000 - 400,000 Q4 98

XC40250 20,102 270,848 160,000 - 500,000 Q4 98

For more information on the XC4000XV family, please contact your localXilinx Sales Office.