Xilinx CORE Generator

Contents

What's New

CORE Generator Overview

CoreLINX
CoreLINX - New Cores and Software Updates
Register For CoreLINX
Request CORE Generator CD

More Information
CORE Solutions Documentation
CORE Solutions Data Book

Xilinx CORE Generator Overview

The Xilinx CORE Generator is a software tool for generating and delivering parameterizable cores optimized for Xilinx FPGAs. Use the CORE Generator to design high-density Xilinx FPGA devices and achieve higher performance results plus a reduction in design time.

CORE Generator Features

Simple, intuitive operation – Select a core, enter parameters, and generate
Compatible with VHDL, Verilog, and Schematic top-level design flows
Cores are delivered with a logic design plus an optimal floorplan or layout
- Performance is independent of FPGA device size
- Performance stays constant as more cores are added
Optimal results as measured against the best hand-packed design
Data sheet and VHDL behavioral model with each core
Ready access to intellectual property from Xilinx and Xilinx partners
Predictable & repeatable results – core performance is specified in advance
PC and Workstation platforms supported

CORE Generator Benefits

Faster time-to-market
- Fast core generation time with proprietary Xilinx software
- Reduced place and route time with pre-placed Cores
- Less engineering required with pre-designed cores
Facilitates design reuse
- Build your design out of cores
- Simpler documentation with larger parameterizable building blocks
Optimal core layout produces lower power dissipation

CORE Generator Smart-IP technology

Xilinx Smart-IP technology produces cores with performance specified in advance. Performance and density (# CLBs) is contained in the core data sheet and is independent of the Xilinx FPGA device size and independent of the number of cores that are installed in a large device. Xilinx Smart-IP technology guarantees that there is no routing interference between multiple cores or between cores and other logic.

No Surprises! – The predictable and repeatable performance allows large FPGA designs to maintain clock speeds as the design process proceeds. If it is necessary to move to a larger device, the core performance does not change.

The core generation process produces the logic for the core, partitions it into configurable logic blocks (CLBs), and then places the CLBs relative to each other. This logic design coupled with a CLB-floor-plan or physical design is what makes our cores predictable. The relative locations are maintained as the core is integrated into the overall design and placed anywhere in a large FPGA.

CORE Generator Components

The CORE Generator contains a library of LogiCORE parameterizable cores, AllianceCORE cores, and data sheets. The LogiCORE category contains cores that are designed and supported by Xilinx, while the AllianceCORE category contains the cores that are designed and supported by our AllianceCORE partners.

CORE Generator Interfaces

The CoreLINX interface permits access to new plug-in cores over the WEB and the SystemLINX interface connects the CORE Generator to system-level tools.

Generating a Core

After defining all of your parameters, simply click on the Generate button. The output is an optimized CORE for the targeted FPGA device with the following files.

A tailored Xilinx netlist with complete relative placement information to guarantee performance VHDL or Verilog instantiation code
A VHDL behavioral model
A symbol for schematic capture tools

CORE Generator Platform Compatibility

CORE Generator V1.4 supports Windows 95, Windows NT, and Solaris 2.5 and 2.6 operating systems for PC and Workstation compatibility. No security keys are required.

New Cores and Core updates

New plug-in cores that are not included on the V1.4 CORE Generator CD can be downloaded from this web site and easily added to the CORE Generator through the CoreLINX interface.

Availability

The CORE Generator V1.4 CD is available at no charge through your local Xilinx representative, or by requesting it here

. You must first obtain a UserID and Password, which can be obtained at the CoreLINX registration

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