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Answers Database
List of Prototyping/configurable computer board manufacturers.
Record #113
Problem Title: Anapolis Micro Systems, Inc. 190 Admiral Cochrane Drive Suite 130 Annapolis, MD 21401 Phone: 410-841-2514 Fax: 410-841-2518 AnnapMicro@aol.com Giga Operations Corp. 2374 Eunice Street Berkeley, CA 94708 Phone: 510-528-8438 Fax: 510-526-6688 E-mail: gigaops@holonet.com Metalithic Systems Inc. 9500 South 500 West Suite 104 Sandy, UT 84070 Phone: 801-561-0114 Fax: 801-561-4702 Virtual Computer Corp. 6925 Canby Avenue, #103 Reseda, CA 91335 Phone: 818-342-8294 Fax: 818-342-0240 E-mail: info@vcc.com ============================================================ System name: ACME (Adaptive Connectionist Model Emulator) FPGA Devices: 14 Xilinx XC4010s and 6 Xilinx XC3195s On-board RAM: 7 4K Dual-ported global memories each 4010 has a 4k Dual-ported memory External bus: SBUS Interconnect: Clos Network between 4010s and 3195s 3195s are used as programmable interconnect among 4010s and with global memory Contact: Pak K. Chan Computer Engineering Board 225 Applied Sciences University of California Santa Cruz, CA 95064 Email: pak@cse.ucsc.edu Notes: See FPGA'94 Berkeley ACM Workshop System name: Anyboard FPGA Devices: 5 Xilinx 3042 On-board RAM: 384K External bus: ISA Interconnect: Fixed buses Contact: David E. Van den Bout ECE Department North Carolina State University Raleigh, NC 27695-7911 Notes: System name: ArMen FPGA Devices: 1 3090 per node. The MIMD/FPGA parallel machine is modular and extensible. On-board RAM: 1, 2 or 4Mb/node each board has a T805 processor with 4 20Mb/s links. External bus: SBUS Archipel board with a T805. I/Os can be handled directly within ArMen using additional transputer/peripheral boards. Interconnect: Processor interconnection is host system dependent. We have two 8 nodes computers configures as cubes. 3090 south and west ports are assembled into a linear ring with 36bits data path. North ports are mapped in the processor address space, so that they receive address/data from their local processor. The FPGA 32 bit south port is free for extensions or input/output on each node. Contact: Bernard Pottier Laboratoire d'Informatique de Brest Universite de Bretagne Occidentale UFR Sciences, BP 802, Brest, 29285, FRANCE. Email: pottier@univ-brest.fr Notes: See Napa FCCM 93 and 94 or Hawai HICSS-94 proceedings. ArMen can easily be connected to any host having an interface board for transputers. There are projects for commercial distribution System name: BORG II FPGA Devices: 2 Xilinx 4003As and 2 Xilinx 4002As On-board RAM: 8K External bus: PC-bus interface in 5th FPGA Interconnect: 4 FPGAs in a Clos network 2 FPGAs can be used as interconnect or logic Contact: Pak K. Chan Computer Engineering Board 225 Applied Sciences University of California Santa Cruz, CA 95064 Email: pak@cse.ucsc.edu Notes: 100 boards made by Xilinx and distributed for educational purposes. FPGAs are socketed and can be replaced by any 4000 series pc84 part. System Name: Chameleon FPGA Devices: 7 Algotronix CAL External Bus: Interconnect: Fixed mesh Contact: Cuno Pfister pfister@cs.inf.ethz.ch Notes: Experimental workstation from ETH Zurich with FPGA's closely coupled to MIPS R3000 processor and innovative object based design software written in the Oberon language. System name: CHAMP (Configurable Hardware Algorithm Mappable Processor) FPGA Devices: 16 Xilinx 4013 On-board RAM: 512K Dual-ported External bus: VME Interconnect: Crossbar (using FPGAs) Contact: Brian Box Lockheed Sanders NCA01-2244 P.O Box 868 Nashua, NH 03060 Phone: (603) 885-7487 FAX: (603) 885-9056 Email: box@nhquax.sanders.lockheed.com Notes: System name: CHS 2x4 FPGA Devices: 9 Algotronix CALs (1 controller + 8 compute) On-board RAM: 2 MB SRAM External bus: ISA Interconnect: Fixed mesh Contact: Tom Kean Xilinx Development Corp.System name: CM-2XFPGA Devices: 16 Xilinx 4005 17100 Science Drive Bowie, MD 20715 Phone: (301) 805-7479 FAX: (301) 805-7602 Phone: cfreese@super.org Notes: A Connection Machine 2 SIMD machine from Thinking Machines Corporation with the Weitek WTL3164 floating point processors replaced by Xilinx 4005s. De-commissioned 1994. System name: DSP-56X FPGA Devices: 1 Xilinx 3042 On-board RAM: 32KW-128KW (shared with DSP56000) External bus: SBus & Flexible Interconnect: See notes below. Contact: Michael C. Peck President Berkeley Camera Engineering 3616 Skyline Drive Hayward, CA 94542-2521 Phone: 510-889-6960 Fax: 510-889-7606 email: mikep@bce.com Notes: The DSP-56X is an SBus card that contains a 40MHz Motorola 5600x family DSP, a Xilinx 3042, and memory (32K words or 128K words I believe). The 3042 sits directly on the 56000 bus and can be accessed from either the 56000 or the SBus. Some of the Xilinx pins are connected to the SBus back panel connector. System name: EVC (The Engineers Virtual Computer) FPGA Devices: 1 Xilinx 4010 On-board RAM: Daughter board (see notes) External bus: SBus Interconnect: None All Interconnect via Xilinx 4010's on G-800 2x32 bit buses and 2x16 bit buses on G-800 Configuration is programmable - Virtual Bus Contact: bovarga@gigaops.com 2374 Eunice St. Berkeley, CA. 94708 Notes: Modules have standard form factor and pinout. All bus lines to G-800 connect via FPGAs. Up to 16 modules of all types on 1 G-800 board. Visual Computing Module (VMC)= 2xXC4005; 4MB DRAM and 80 MIPS DSPS PGA10MOD = 1 x XC4010, 2MB DRAM, 128K SRAM PROTOMOD = same as PGA10MOD with pinouts extended to pads for wirewrap, logic analyzer, etc. 16xVCMs = 32 XC4005's, 2 XC4010's on G-800, 64 MB DRAM 16xPGA10MODs = 16 XC4010's, 2 XC4010's on G-800, and 32 MB DRAM and 2 MB SRAM XPGAMOD = 4xXC4010, 8 MB DRAM, 512K SRAM (available Oct) 16xXPGAMODs = 32 XC4010's, 2 XC4010's on G-800, and 128 MB DRAM and 8 MB SRAM System name: GANGLION FPGA Devices: 24 Xilinx 3090 On-board RAM: 24K PROM External bus: VME / Datacube MAXbus Interconnect: Fixed Contact: Charles Cox IBM Research Division Almaden Research Center San Jose, CA 95120-6099 Notes: Used exclusively for neural networks. System name: HARP1 FPGA Devices: 1 Xilinx 3195 On-board RAM: 64K SRAM / 4MB DRAM External bus: 4 x 20Mbit/sec transputer links + expansion port (spare FPGA pins) Interconnect: None Contact: Ian Page Oxford University Computing Laboratory, Wolfson Building, Parks Road, Oxford OX1 3QD, U.K. +44 1865 273853 FAX: +44 1865 273839 EMail : Ian.Page@comlab.ox.ac.uk Notes: The HARP1 is an industry standard TRAM board (size 6 = 165 x 84mm) containing a 32-bit RISC-style microprocessor (a T805 transputer) with 4 Mbytes of dynamic RAM. Two independent banks of 32K x 16-bit fast static RAM are attached to the Xilinx 3195 Field Programmable Gate Array. The FPGA has full access to the microprocessor bus. A 100MHz frequency synthesiser is used for arbitrary clock generation. An expansion port is connected to the spare FPGA pins. TRAM motherboards allow for easy integration into a variety of host systems, or for connecting multiple HARP boards together. For more information see: http://www.comlab.ox.ac.uk/oucl/people/ian.page.html Department of Electrical Engineering Toronto, Canada Email: lewis@eecg.toronto.edu Notes: Marc-1 consists of two modules. Each module contains an instructions unit of 3 Xilinx 4005s, a datapath of 6 Xilinx 4005s, a 256K x 64 instruction memory, a 256K x 32 data memory and a Weitek 3364. These are connected by an interconnect module of 5 Xilinx 4005s. Two more Xilinx 4005s are used to interface to the Sun Sparc host. System name: Mushroom FPGA Devices: 7 Xilinx 3090 On-board RAM: 5Mb 35ns static RAM External bus: VME (Sun 3/110 as host) Interconnect: Fixed busses Contact: Mario Wolczko now at : Sun Microsystems Labs, Mario.Wolczko@sun.com or Ifor Williams now at: ADC, 100140.2651@CompuServe.COM Project was based at the University of Manchester, England, 1987-92. Notes: See: `Using FPGAs to Prototype New Computer Architectures,' Ifor Williams, in `FPGAs', Abingdon EE&CS Books, edited by Will R Moore and Wayne Luk, 1991, pp 373-382. Mushroom was a prototypical implementation of a RISC architecture designed to support dynamic object-oriented languages. System name: nP (The Nano Processor) FPGA Devices: 2 Xilinx 3090 On-board RAM: 64K SRAM / 1M DRAM External bus: ISA Interconnect: Fixed Contact: National Technology, Inc. 9500 South 500 West Suite #104 Sandy, UT 84070 Phone: (801) 561-0114 FAX: (801) 561-4702 Email: wirthlin@gecko.ee.byu.edu Notes: System name: PAM (Programmable Active Memories) (perle-0) FPGA Devices: 25 Xilinx 3020 On-board RAM: 0.5 MB External bus: VME Interconnect: Fixed mesh Contact: Patrice Bertin Paris Research Laboratory Digital Equipment Corporation 85, avenue Victor Hugo 92500 Rueil-Malmaison, France bertin@prl.dec.com Notes: Replaced by the DEC PAM perle-1. System name: PAM (Programmable Active Memories) (PeRLe-1) FPGA Devices: 24 Xilinx 3090 On-board RAM: 4MB SRAM External bus: DEC TURBOchannel Interconnect: Fixed mesh Contact: Patrice Bertin Paris Research Laboratory Digital Equipment Corporation 85, avenue Victor Hugo 92500 Rueil-Malmaison, France bertin@prl.dec.com Notes: Set the record for RSA encryption in 1990. System name: PRISM (Processor Reconfiguration through Instruction Set Metamorphosis) FPGA Devices: 4 Xilinx 3090 On-board RAM: None External bus: 16 bit Interconnect: None Contact: Mike Wazlowski or Harvey Silverman Laboratory for Engineering Man/Machine Systems Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Notable for its use of C as the description language
for the programmable logic.
System name: PRISM-II (Processor Reconfiguration through Instruction Set Metamorphosis) FPGA Devices: 3 Xilinx 4010 per processing node On-board RAM: 128K x 32 per 4010 External bus: 64 bit writes, 32 bit reads, on processor bus (it's not external) Interconnect: Inverted tree, or none, application selectable Contact: Mike Wazlowski or Harvey Silverman Laboratory for Engineering Man/Machine Systems Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Each PRISM-II board is a node in the Armstrong III
loosely-coupled parallel processor. The host CPU is a
33Mhz AMD Am29050 RISC processor. There are 20 nodes
that are connected by a reconfigurable (of course)
interconnection topology.
System name: R16 and RISC4005 FPGA Devices: 1 Xilinx XC4005 On-board RAM: 64K Words (16 bit words) External bus: R16 bus, 16 bit addr, 16 bit data, Synchronous at 20 MHz Interconnect: Any Contact: Philip Freidin Fliptronics 468 S. Frances St, Sunnyvale, CA 94086 Phone: (408) 737-8060 or at Xilinx (408) 879-5180 email: philip@xilinx.com Notes: A 16 bit RISC processor that requires 75% of an XC4005, 16 general registers, 4 stage pipeline, Target speed is 20 MHz. Can be integrated with peripherals on 1 FPGA, and ISET can be extended. System name: Rasa Board FPGA Devices: 3 Xilinx 4010 On-board RAM: 320K SRAM External bus: ISA Interconnect: 2 Aptix FPICs Contact: Herman Schmit ECE Department Carnegie Mellon University Pittsburgh, PA 15213 Phone: (412) 268-2476 Notes: Integrated with a behavioral synthesis tool which allows specification of the desired algorithm in behavioral Verilog or C. System name: SPARXIL FPGA Devices: 3 Xilinx XC4010s On-board RAM: 2 256Kx32bit SRAMs for user data 1 128Kx8bit SRAM for on-board configuration cache External bus: SBus Interconnect: fixed Contact: Andreas Koch Institut f"ur theoretische Informatik Abteilung Entwurf Integrierter Schaltungen Gaussstr. 11 D-38106 Braunschweig, Germany Email: a.koch@tu-bs.de Notes: See FPL'93 Oxford workshop System name: SPACE (Scalable Parallel Architecture for Concurrency Experiments) FPGA Devices: 16 Algotronix CAL On-board RAM: External bus: Custom Interconnect: Fixed grid Contact: George Milne HardLab Department of Computer Science University of Strathclyde Glasgow G1 1XH Scotland, UK Notes: Used for physics research. System name: Spyder FPGA Devices: 5 Xilinx 4003, 2 Actel A1280 On-board RAM: 128K SRAM plus 2K fast registers External bus: VME and Sun SBus Interconnect: Fixed Contact: Christian Iseli Logic Systems Laboratory Swiss Federal Institute of Technology CH-1015 Lausanne Switzerland Email: chris@lslsun.epfl.ch Notes: A reconfigurable VLIW machine. System name: SPLASH FPGA Devices: 32 Xilinx 3090 On-board RAM: 4 MB SRAM External bus: VME Interconnect: Linear array Contact: Jeffrey M. Arnold IDA Supercomputing Research Center 17100 Science Drive Bowie, MD 20715 Phone: (301) 805-7479 FAX: (301) 805-7602 Phone: jma@super.org Notes: Replaced by SPLASH 2. System name: SPLASH 2 FPGA Devices: 16 Xilinx 4010 On-board RAM: 8 MB External bus: Sun SBus Interconnect: Linear array plus crossbar Contact: Jeffrey M. Arnold IDA Supercomputing Research Center 17100 Science Drive Bowie, MD 20715 Phone: (301) 805-7479 FAX: (301) 805-7602 Phone: jma@super.org Notes: System name: TbC-Pamette (PAM - Programmable Active Memories) FPGA Devices: 1 to 4 Xilinx 40XX in PQ-208 package Currently supported configurations: 4010 + 4003H 4 x 4010 On-board RAM: Daughter board (see notes) External bus: DEC TURBOchannel Interconnect: Fixed mesh 2 x 2 matrix Contact: Mark Shand Paris Research Laboratory Digital Equipment Corporation 85, avenue Victor Hugo 92500 Rueil-Malmaison, France shand@prl.dec.com Notes: 128 user I/O to daughter board. Synchronous RAM daughter board is under development. Pamette is targeted as a generic I/O adapter with local compute capability. System name: TM-1 (Transmogrifier 1) FPGA Devices: 4 Xilinx 4010 On-board RAM: 4 32Kx9 SRAMs External bus: custom to SUN workstation Interconnect: entirely programmable using Aptix AX1024 FPIC Contact: Jonathan Rose Dept. of Electrical and Computer Engineering University of Toronto 6 King's College Road Toronto, Ontario Canada M5S 1A1 Email: jayar@eecg.toronto.edu Notes: Intended more for rapid prototyping of circuits, but can be used for computing. System name: VZ80 (Pin compatible replacement for the Zilog Z80 8 bit uP) FPGA Devices: 2 Xilinx 4013s On-board RAM: Not applicable External bus: 40 Pin DIP socket to any Z80 motherboard (ex:TRS-80) Interconnect: Fixed wire wrapped interconnect Contact: Gregory Recupero VAutomation Inc. 71 Spit Brook Rd. Suite 306 Nashua NH 03060 Email: greg@VAutomation.com Notes: From synthesizable VHDL model available from VAutomation. System name: V6502 (Pin compatible replacement for the Rockwell 6502 8 bit uPFPGA Devices: 1 Xili nx 4013 On-board RAM: Not applicable External bus: 40 Pin DIP socket to any 6502 motherboard (ex:AppleII-C) Interconnect: Fixed wire wrapped interconnect Contact: Eric Ryherd VAutomation Inc. 71 Spit Brook Rd. Suite 306 Nashua NH 03060 Email: eric@VAutomation.com Notes: From synthesizable VHDL model available from VAutomation. System name: The Virtual Computer (P-Series) FPGA Devices: Up to 52 Xilinx 4013 On-board RAM: Up to 8 MB SRAM, 256K dual-ported SRAM External bus: Bus Independent - Current SBus interface Interconnect: Up to 24 ICUBE FPID Contact: Steve Casselman Virtual Computer Corporation Reseda, CA 91335 Phone: (818) 342-8294 FAX: (818) 342-0240 Email: sc@vcc.com Notes: The Virtual Computer P-Series consists of P1, P2, P3 and P4. The P1 has 14 4013s the P2 26 4013s the P3 40 4013s and the P4 has 52 4013s. System name: X-12 FPGA Devices: 12 Xilinx 3195 On-board RAM: 384K SRAM (32K per FPGA) External bus: ISA Interconnect: Fixed common bus Contact: National Technology, Inc. 9500 South 500 West Suite #104 Sandy, UT 84070 Phone: (801) 561-0114 FAX: (801) 561-4702 Email: wirthlin@gecko.ee.byu.eduNotes: Contact: Steve Casselman Virtual Computer Corporation Reseda, CA 91335 Phone: (818) 342-8294 FAX: (818) 342-0240 Email: sc@vcc.com Notes: The EVC is a single FPGA based transformable computing system. It has a daughter board area that has 96 user I/O from the 4010. A 2 Meg fast SRAM daughter board is available now. System Name: G-800 System FPGA Devices: Grouped in modules (maximum 16 -- see Notes below) On-board RAM: See Notes below External Bus: VESA (VL) Local bus VESA Media Channel - 100 MB/sec video bus 80 pin connector supports 32 bit devices Interconnect: Bus Oriented Communication - Virtual Bus 53 Mortonhall Gate Edinburgh EH16 6TJ Phone: 44 31 666 2600ext204 Fax: 44 31 666 0222 Email: tomk@xilinx.com Notes: Based on work at the University of Edinburgh by Tom Kean and John Gray. Commercialized by Algotronix. Algotronix purchased by Xilinx in 1993. System cascadable to 2 boards. No longer commercially available. End of Record #113 - Last Modified: 11/06/96 02:46 |
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