Answers Database


ViewSim: Global reset signal names for 2k, 3k, 4k, 5k, 7k, and 9k (startup)


Record #128

Product Family: Software

Product Line: ViewLogic

Product Part: viewsim

Product Version: 7.5

Problem Title:
ViewSim: Global reset signal names for 2k, 3k, 4k, 5k, 7k, and 9k (startup)


Problem Description:

Urgency:    Standard

General Description:
      The first step when simulating a design in PROsim or ViewSim is to initialize
all the flip-flops. To do this, the global set/reset signal must be asserted, time simulated, and the global set/reset signal de-asserted. The global signal is attached to all the flip-flop simulation models and therefore must be used during both
functional and timing simlations.


Solution 1:

The following is a table of global set/reset signals and their polarities:

     Family   Signal   Operation   Active
     ------------------------------------
     XC2000    GR	Reset	    Low
     XC3000    GR	Reset	    Low
XC4000 GSR Set/Reset High
XC5200 GR Reset High
XC7000 PRLD Set/Reset High
XC9500 PRLD Set/Reset High

NOTE: The operation is based on the type of flip-flop that has been used.
For XC2000, XC3000, and XC5200 designs, only reset flip-flops can be used.
For XC4000, XC7000, and XC9500 designs, either set or reset flip-flops can
be used.

The following demonstrates how to assert a global signal for an XC3000 device:

Viewsim>> l GR
Viewsim>> sim 100ns
Viewsim>> h GR

If you do not assert the appropriate global set/reset signal, all the flip-flops in the design will not function properly. All the outputs will have the value `X'
which is the `UNKNOWN' value. It is also recommended that all of your
external signals are assigned before the reset is asserted.

This solution applies to all Viewlogic simulation tools. It also does not
matter if you have the "STARTUP" block included in the design.



Solution 2:

      When a design has been brought through NGDBUILD in the Xilinx M1 tools, warnings
will be issued if the "STARTUP" block is not included. The warning
messages are as follows:

WARNING:basnu:110 - NOTE: This design contains the undriven net "GSR" which you
  must drive during simulation to get valid results.

WARNING:basnu:110 - NOTE: This design contains the undriven net "GTS" which you
  must drive during simulation to get valid results.

      With the "STARTUP" block not included, the GSR(Global set/reset) signal needs to
be asserted and de-asserted as in Solution 1 for both functional and timing simulations. The GTS(Global 3-State Control) signal does not need to be driven during simulation. This signal will be forced low during simulations.
      However, on designs that INCLUDE the "STARTUP" block, there will be additional
steps to perform when simulating a design. The additional step is to drive the GTS signal Low. The following demonstrates how to assert the GTS LOW:

Viewsim>> l GTS

      If you do not assert the GTS signal, the all the IOB outputs will have the value
'X' which is the 'UNKNOWN' value. IOB outputs include OBUF's and OFD's.




End of Record #128 - Last Modified: 02/06/98 14:07

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!