Answers Database
FPGA Configuration: time to get off D7 after rs, before RDY/BUSY in async periph
Record #157
Problem Title:
FPGA Configuration: time to get off D7 after rs, before RDY/BUSY in async periph
Problem Description:
Solution 1:
In the XC4000 asynchronous peripheral mode, the D7 input data bit doubles as
a Ready/Busy signal output, when the Read Strobe signal is asserted. Users
have approximately 50ns to remove all signals that drive D7 after asserting
read strode, or contention could result.
End of Record #157 - Last Modified: 04/22/96 10:00 |
