Answers Database
SYN2XNF: issues ERROR 220: 'can't find &__logic_1__.map'
Record #198
Problem Title:
SYN2XNF: issues ERROR 220: 'can't find &__logic_1__.map'
Problem Description:
Solution 1:
When Invoking syn2xnf on a .sxnf or .sedif file, Syn2xnf may issue an error
similar to the following:
ERROR 220: Can't open file 'User's_DS401_dir/data/xsi/xunmap_3000/
&__logic_1__.map'
Warning 285:
Binding mismatch on pin __LOGIC_1_PIN__ in symbol CBSCNTRLWIR/ARBITOR/U208,
file 8847.xnf
The most likely scenario when this occurs is using Synopsys Design Compiler
with the design output file is in EDIF format.(a .sedif file written by Design
Compiler). Syn2xnf will execute 2 commands if the design is in EDIF
format--EDIF2XNF and XNFMERGE. If the design is a .sxnf file (written out by
Synopsys FPGA Compiler), only XNFMERGE is executed. The error occurs when
XNFMERGE is executing.
Answers:
1) Xnfmerge is NOT looking for a .map file. It's actually looking for a
.xnf file in the $XACT/data/xsi/xunmap_3000 directory: the
&__logic_1__.xnf file.
2) Add the following 4 lines in the .synopsys.dc_setup file. (this file is
like Xilinx's xactinit.dat file. Each time Synopsys Compiler is invoked, it
will read the .synopsys.dc_setup file. (.synopsys file is the same)
edifout_power_name = "pwr"
edifout_power_pin_name = "pwr"
edifout_ground_name = "gnd"
edifout_ground_pin_name = "gnd"
Then, recompile the design in Synopsys again.
3) If the solution above doesn't work, create the &__logic_1__.xnf file.
(IF XNFMERGE can't open &__logic_0__.map, then create &__logic_0__.xnf file)
Steps to create the &__logic_1__.xnf file.
I) cp DS401_dir/data/xsi/xunmap_3000/pwr.xnf '&__logic_1__.xnf'
II) vi '&__logic_1__.xnf' to edit the XNF file as followed:
LCANET, 4
PROG, GENLIB2XNF, V1.00, "Tuesday May 5, 1992 10:2:39"
PWR, 1, __logic_1_pin__
EOF
NOW xnfmerge should be able to find &__logic_1__.xnf file in the user's
current directory.
This problem has been fixed in XSI 5.2.
End of Record #198 - Last Modified: 01/10/96 16:21 |
