Answers Database
FPGA CONFIGURATION: How to handle slow Vcc rise time, brown out problems
Record #202
Problem Title:
FPGA CONFIGURATION: How to handle slow Vcc rise time, brown out problems
Problem Description:
Solution 1:
Q. How should reset and d/p be handled if you have
slowly rising Vcc?
A. Hold RESET low until Vcc rises above 4V.
Q. How should reset and d/p be handled if you need to
recover from a dip in power?
A. Wait for Vcc to rise to 4V. Once it does, pull RESET High for 6us
(the 1us stated in the 1993 data book is a typo),
then pull both RESET and D/P Low for another 6us. To simplify the
required circuit to recover from power glitches, you could tie D/P low
permanently and omit the pullup on it if you are not going to do
a logical RESET of the device. Power watchdog circuits are available
from vendors such as Maxim for monitoring supply levels.
The above applies only to XC3000 family parts.
End of Record #202 - Last Modified: 11/04/96 05:28 |
