Answers Database
VHDL: Implementing the XC3000/XC4000 readback function.
Record #226
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Problem Title:
VHDL: Implementing the XC3000/XC4000 readback function.
Problem Description:
How to implement the Readback function in VHDL ?
Solution 1:
The following is an example instantiation of the readback
function in VHDL. This example assumes that the readback
clock is cclk.
entity readbk is
port(trig: in bit;
data, rip: out bit);
end readbk;
architecture inst of readbk is
component RDBK
port(trig: in bit;
data, rip: out bit);
end component;
begin
U1: RDBK port map(trig, data, rip);
end inst;
End of Record #226 - Last Modified: 05/30/96 14:59 |
