Answers Database XDELAY 5.2: Correlating delays through TBUFs with data book values Record #370 Product Family: Software Product Line: XACT FPGA Product Part: xdelay Product Version: 5.2 Problem Title: XDELAY 5.2: Correlating delays through TBUFs with data book values Problem Description: Solution 1: How to correlate delays through TBUFs as reported by Xdelay, with those in the Data Book: At first glance it may appear that the delays through TBUFs, as reported by XDELAY do not correspond with those in the data book. They do. The confussion stems from the fact that Xdelay lumps part of the delay through it into the routing delay through the long line. For example, an Xdelay report such as: From: Blk P109 PAD to P109.I2 : 3.0ns ( 3.0ns) Thru: Net enable to TBUF_R24C24.1.T : 18.8ns ( 21.8ns) Thru: Blk TBUF_R24C24.1 to TBUF_R24C24.1.O : 5.3ns ( 27.1ns) Thru: Net long0 to P46.O : 8.4ns ( 35.5ns) To: O pin to PAD, Blk P46 : 7.0ns ( 42.5ns) may seem to indicate that the delay from the T to the O pin of the TBUF is only 5.3ns, while Ton for the example should have been 12.6ns (XC4013). The total delay from this TBUF's T pin to the pad is 5.3 + 8.4 = 13.7ns which accounts for (Ton + Routing on the Long line) = (12.6 + 1.1) = 13.7ns Depending on the application, the delay from the T pin to a stable long line logic level may be longer than reported by Xdelay. In reporting the delay from the T pin to stable data at the Long line, Xdelay uses the Ton parameter, which assumes that a TBUF drives the long line at any given time. If the long line is left floating, and its floating value (pulled up '1') used as valid data, the delay from a Low at the TBUF's T pin to a valid logic '1' is longer than reported by Xdelay. The four parameters which describe the delay from the T pin of a TBUF to its O pin are (see 1994 Data Book, p.2-50): Ton: T going Low to Long Line going from resistive pullup to driving active Low. Toff: T going High to TBUF going tri-state. Tpus: T going High to Long line going from Low to High, pulled by single        resistor. Tpuf: T going High to Long Line going from Low to High, pulled by two resistors. Tpuf should be used (instead of Ton) whenever the long line has two pullups on it (ppr applies two pullups to any long line running the width of the chip), and the pulled up logic '1' is used as valid data. Tpus, should be used whenever there is only one pullup on a long line running the width of the chip (single pullups can only be applied by hand in EditLca on any long line running the width of the chip). In the case of a Wired-And, Xdelay DOES show the appropriate delays. Also notice that simulation does "the right thing" (shows the appropriate delays) for all cases (wand, tri-state buses, etc.) End of Record #370 - Last Modified: 11/15/96 18:39

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!