Answers Database
2.1i: NGD2EDIF: WARNING:NgdHelpers:33 - NOTE: This design contains the undriven net "PRLD"
Record #414
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2edif
Product Version: 2.1i
Problem Title:
2.1i: NGD2EDIF: WARNING:NgdHelpers:33 - NOTE: This design contains the undriven net "PRLD"
Problem Description:
Urgency: Standard
General Description:
This warning appears during NGD2EDIF (timing netlist generator)
WARNING:NgdHelpers:333 - NOTE: This design contains the undriven net "PRLD"
which you could drive during simulation to get valid results.
writing EDIF file to 'time_sim.edn' ...
Solution 1:
When a 9500* powers up, the registers can be preloaded with a value
if the register is given an INIT=S property. If no init properties
are assigned, all registers in the 9500* will power up with a 0 value.
In the fitter report, this is listed as .PRLD - short for preload.
Each register will have a .PRLD, and it will be set to GND unless
you initialize it, in which case it will be set to VCC.
In order to simulate this preload on power-up, the PRLD signal
needs to be toggled to set the registers in their proper
power-up state. This warning is in regards to timing simulation
only and has no effect on physical device operation.
*9500/XL/XV
End of Record #414 - Last Modified: 01/05/00 12:57 |
