Answers Database Obsolete: XC7000, SYNOPSYS FPGA/Design Compiler: Example .synopsys_dc.setup file Record #538 Product Family: Software Product Line: Synopsys Product Part: xc7000 Synopsys Libraries Problem Title: Obsolete: XC7000, SYNOPSYS FPGA/Design Compiler: Example .synopsys_dc.setup file Problem Description: Here is an example of a .synopsys_dc.setup file for the XC7000 family using Synopsys' Design Compiler or FPGA Compiler. Solution 1: Here is an example of a .synopsys_dc.setup file for the XC7000 family using Synopsys' Design or FPGA Compiler. NOTE: You MUST have the .synopsys_vss.setup file also in this directory, for compiler to find the location of the XC7000 library. /* Design Compiler and FPGA Compiler startup file - .synopsys_dc.setup */ /* for XC7000 EPLD */ /* Insert actual $DS401 and $SYNOPSYS path into search_path below */ search_path = {. \              <DS401-XACT-Directory>/synopsys/libraries/syn \              <SYNOPSYS-Directory>/libraries/syn} link_library = {xc7000.db xc7000.sldb} target_library = {xc7000.db} symbol_library = {xc7000.sdb} synthetic_library = {xc7000.sldb} bus_naming_style = "%s<%d>" bus_dimension_separator_style = "><" bus_inference_style = "%s<%d>" edifout_netlist_only = true edifout_power_and_ground_representation = cell edifout_write_properties_list = {LOC} compile_fix_multiple_port_nets = true xnfout_library_version = "2.0.0" /* Useful aliases for EPLD design processing */ alias a analyze -format vhdl alias e elaborate alias c compile -map_effort low alias sp set_port_is_pad alias ip insert_pads alias s set_attribute alias wx write -format xnf -hierarchy -output End of Record #538 - Last Modified: 05/04/99 10:43

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