Answers Database PPR 5.2.0, 4000E: Data read during Dual Port RAM simultaneous read and write is incorrect Record #677 Product Family: Software Product Line: XACT FPGA Product Part: ppr Product Version: 5.2 Problem Title: PPR 5.2.0, 4000E: Data read during Dual Port RAM simultaneous read and write is incorrect Problem Description: In the 4000E architecture, when the CLB is configured as Dual Port RAM, the F function generator is used to decode the READ address, while the G function generator is used to decode the WRITE address.    There is a fixed ordering relationship between the address lines connected to the F and G function   generators that must be preserved. If pin F1 on the F function generator is connected to address l ine addr1, and pin F2 is connected to address line addr2, then G1 on the G function generator must be connected to addr1, and G2 to addr2. This ensures that simultaneous READs and WRITEs to the same   address actually reference the same address. However, in 4000E designs routed by PPR pre-5.2.0w, READs done during a Dual Port RAM (DPRAM) simult aneous read and write operation to the same address may yield incorrect data. This is because durin g the placement and routing of the design, PPR pre-5.2.0w may swap the DPRAM address pins on the F and G function generators in an inconsistent manner--i.e., a swap of addr1 from F1 to F2 does not al so force a swap of addr1 from G1 to G2. As a result, the actual address being read from ends up be ing different from the WRITE address, and the RAM outputs data from the wrong address. Solution 1: The problem is fixed in PPR pre-5.2.1c, with the additional requirement that you must also create an   xactinit.dat file in your PPR run directory and add the following line to it:        mdmake_pin_lock_level = 2. End of Record #677 - Last Modified: 04/11/96 14:05

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